HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 322

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 User Break Controller
9.2.10
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2
break is issued when the break condition is satisfied after BETR becomes H'0001.
Note: When the instruction fetch cycle is specified as the break condition of the channel B, and its
Rev. 1.00 Dec. 27, 2005 Page 278 of 932
REJ09B0269-0100
Bit
15 to 12
11 to 0
Instruction
RTE
DMULS.L Rm,Rn
DMULU.L Rm,Rn
MAC.L @Rm+,@Rn
MAC.W @Rm+,@Rn
MUL.L Rm,Rn
AND.B #imm,@(R0,GBR)
OR.B #imm,@(R0,GBR)
TAS.B @Rn
TST.B #imm,@(R0,GBR)
XOR.B #imm,@(R0,GBR)
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC Rm,SSR
LDC Rm,SPC
LDC Rm,R0_BANK
LDC Rm,R1_BANK
LDC Rm,R2_BANK
LDC Rm,R3_BANK
LDC Rm,R4_BANK
LDC Rm,R5_BANK
LDC Rm,R6_BANK
LDC Rm,R7_BANK
break condition is triggerd by the following instructions, the BETR is decrimented by the
following value (not by one).
Execution Times Break Register (BETR)
Bit Name

BET11 to
BET0
12
Initial
Value
All 0
All 0
– 1 times. When a break condition is satisfied, it decreases BETR. A
Decrement value
4
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Execution Times
Instruction
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,R0_BANK
LDC.L @Rm+,R1_BANK
LDC.L @Rm+,R2_BANK
LDC.L @Rm+,R3_BANK
LDC.L @Rm+,R4_BANK
LDC.L @Rm+,R5_BANK
LDC.L @Rm+,R6_BANK
LDC.L @Rm+,R7_BANK
LDC.L @Rn+,MOD
LDC.L @Rn+,RS
LDC.L @Rn+,RE
LDC Rn,MOD
LDC Rn,RS
LDC Rn,RE
BSR label
BSRF Rm
JSR @Rm
Decrement value
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2