HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 763

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.4.6
MII registers in the PHY-LSI are accessed via this LSI’s PHY interface register (PIR). Connection
is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.
MII Management Frame Format: The format of an MII management frame is shown in figure
18.8. To access an MII register, a management frame is implemented by the program in
accordance with the procedures shown in MII Register Access Procedure.
[Legend]
PRE:
ST:
OP:
PHYAD:
REGAD:
TA:
DATA:
IDLE:
Access Type
Item
Number of bits
Read
Write
Accessing MII Registers
32 consecutive 1s
Write of 01 indicating start of frame
Write of code indicating access type
Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI address.
Write of 0001 if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI register address.
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) performed
16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performed
(b) Read: Bus already released in TA; control unnecessary
PRE
1..1
1..1
32
Figure 18.8 MII Management Frame Format
ST
01
01
2
OP
10
01
2
MII Management Frame
PHYAD
00001
00001
5
REGAD
RRRRR
RRRRR
5
Rev. 1.00 Dec. 27, 2005 Page 719 of 932
Section 18 Ethernet Controller (EtherC)
TA
Z0
10
2
DATA
D..D
D..D
16
REJ09B0269-0100
IDLE
X