HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 78

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
Rev. 1.00 Dec. 27, 2005 Page 34 of 932
REJ09B0269-0100
Notes: *1 The R0 register is used as an index register in indexed register indirect addressing mode
*2 Bank register
*3 Bank register
*4 Bank register
and indexed GBR indirect addressing mode.
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
31
(a) User mode register
configuration
Figure 2.3 Register Configuration in Each Processing Mode
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1,*2
*2
*2
*2
*2
*2
*2
*2
0
31
(b) Privileged mode register
configuration (RB = 1)
R0_BANK1
R0_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1,*3
*1,*4
*3
*3
*3
*3
*3
*3
*3
*4
*4
*4
*4
*4
*4
*4
0
31
(c) Privileged mode register
configuration (RB = 0)
R0_BANK0
R0_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1,*4
*1,*3
*4
*4
*4
*4
*4
*4
*4
*3
*3
*3
*3
*3
*3
*3
0