HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 48

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview and Pin Function
• Supports power-down modes:
• A single channel on-chip watch dog timer
Bus state controller (BSC):
• Physical address space is divided into eight areas: area 0, areas 2 to 4; each a maximum of 64
• The following features are settable for each area.
• Outputs chip select signal (CS0, CS2 to CS4, CS5A/B, and CS6A/B) for corresponding area
Direct memory access controller (DMAC):
• Six channels. Two of these channels (ch0 and ch1) support external requests.
• Supports burst mode and cycle-stealing mode
Timer unit (TMU):
• 3-channel auto reload 32-bit on-chip timer
• 4 types of counter input clocks can be selected
Realtime clock (RTC)*
• On-chip clock, calendar, and alarm
• On-chip 32 kHz crystal oscillator with 1/256-second resolution (interrupt cycle)
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REJ09B0269-0100
Sleep mode
Software standby mode
Module standby mode
Watchdog timer mode and interval timer mode is selectable.
An interrupt can be generated in interval timer mode.
Mbytes, and areas 5A, 5B, 6A, 6B; each a maximum of 32 Mbytes.
Bus size (8, 16 or 32 bits): The supported bus size differs for each area.
Number of access wait cycles: Numbers of wait-state cycles during reading and writing are
independently selectable for some areas.
Setting of idle wait cycles: For the same area or different area.
Specifying the memory to be connected to each area enables direct connection to SRAM,
SRAM with byte selection, burst ROM (synchronization/asynchronous), SDRAM and
PCMCIA.
(The CS assert/negate timing can be selected by software.)
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