HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 605

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.4.2
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time. Figure 16.2 shows the
general format of asynchronous serial communication.
In asynchronous serial communication, the communication line is normally held in the mark
(high) state. The SCIF monitors the line and starts serial communication when the line goes to the
space (low) state, indicating a start bit. One serial communication character consists of a start bit
(low), data (LSB first), parity bit (high/low), and stop bit (high), in this order. In asynchronous
mode, the SCIF synchronizes at the falling edge of the start bit during reception. The SCIF
samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Therefore, communication data is latched at the center of each bit.
Serial
data
1
Serial Operation in Asynchronous Mode
Start
1 bit
bit
0
Figure 16.2 Data Format in Asynchronous Communication
(Example of 8-Bit Data with Parity and 2 Stop Bits)
D0
D1
One unit of communication data (character or frame)
D2
Transmit/Receive data
7 bits or 8 bits
D3
Section 16 Serial Communication Interface with FIFO (SCIF)
D4
D5
Rev. 1.00 Dec. 27, 2005 Page 561 of 932
D6
D7
1 bit or
Parity
no bit
0/1
bit
Idle state (mark state)
1
Stop bit
REJ09B0269-0100
1 bit or
2 bits
1
1

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