HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 603

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16.4
16.4.1
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character, and in clock synchronous mode, in which synchronization is
achieved with clock pulses.
16-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed. Also, the RTS and CTS
signals are included as modem control signals. Transfer format is selected by SCSMR. This is
shown in table 16.3. The SCIF clock source is determined by the combination of the C/A bit in
SCSMR and the CKE1 and CKE0 bits in SCSCR. This is shown in table 16.4.
Asynchronous Mode
• Data length: Choice of 7 or 8 bits
• Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
• Detection of framing errors, parity errors, overrun errors, receive-FIFO-data-full state, receive-
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• The SCIF clock source: Choice of internal or external clock
Clock synchronous Mode
• Transfer format: Fixed to 8-bit data
• Detection of overrun errors during reception
• The SCIF clock source: Choice of internal or external clock
determines the transfer format and character length)
data-ready state, and breaks, during reception
When internal clock is selected: The SCIF operates on the baud rate generator clock.
When external clock is selected: Clock with frequency16 times the bit rate must be input. (The
on-chip baud rate generator is not used.)
When internal clock is selected: The SCIF operates on the baud rate generator clock and
outputs the synchronous clock
When external clock is selected: The SCIF operates on the input synchronous clock. The on-
chip baud rate generator is not used.
Operation
Overview
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Dec. 27, 2005 Page 559 of 932
REJ09B0269-0100