HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 647

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.3.8
SISTR shows the SIOF state. Each of the bits of this register becomes an SIOF interrupt source
when the corresponding bit in SIIER is set to 1. SISTR is initialized by a power-on reset or
software reset.
Bit
15
14
13
12
Bit Name
—
TCRDY
TFEMP
TDREQ
SIOF Status Register (SISTR)
Initial
Value
0
0
0
0
R/W
R
R
R
R
Description
This bit is always read as 0. The write value should always be
0.
This bit indicates a state of the SIOF. If SITCR is written, the
SIOF clears this bit. This bit is valid when the TXE bit in SICTR
is set to 1. If the issue of interrupts by this bit is enabled, the
SIOF issues a control interrupt. If SITCR is written when this
bit is cleared to 0, SITCR is over-written and the previous
contents of SITCR are not output from the TXD_SIO pin.
0: Indicates that a write to SITCR is disabled
1: Indicates that a write to SITCR is enabled
Note: When using this bit, see 2 in section 17.5, Usage Notes.
This bit indicates a state; if SITDR is written, the SIOF clears
this bit. This bit is valid when the TXE bit in SICTR is 1. If the
issue of interrupts by this bit is enabled, the SIOF issues a
control interrupt.
0: Indicates that transmit FIFO is not empty
1: Indicates that transmit FIFO is empty
A transmit data transfer request is issued when the empty
space in the transmit FIFO exceeds the size specified by the
TFWM bit in SIFCTR. This bit is valid when the TXE bit in
SICTR is 1. This bit indicates a state of the SIOF. If the size of
empty space in the transmit FIFO is less than the size
specified by the TFWM bit in SIFCTR, the SIOF clears this bit.
If the issue of interrupts by this bit is enabled, the SIOF issues
a transmit interrupt.
0: No transfer request
1: Transfer request
Reserved
Transmit Control Data Ready
Transmit FIFO Empty
Transmit Data Transfer Request
Rev. 1.00 Dec. 27, 2005 Page 603 of 932
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100