HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 47

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Cache memory:
• 32-kbyte cache, mixture of instructions and data
• 512-entry, 4-way set associative, 16-byte block length
• Write-back, write-through, LRU replacement algorithm
• 1-stage write-back buffer
X/Y memory:
• Three independent read/write ports
• A total of 16 kbytes memory (8-kbyte RAM each for X- and Y-memory)
Interrupt controller (INTC):
• Supports seven external interrupt pins (NMI, IRQ5 to IRQ0)
• Supports fifteen level interrupt pins (IRL3 to IRL0)
• Supports one interrupt request output pin (IRQOUT)
• On-chip peripheral interrupt: Priority level is independently selected for each module
• Supports software vector mode
• Selection of falling/rising/high/low
User break controller (UBC):
• Address, data value, access type, and data size are available for setting as break conditions
• Supports the sequential break function
• Two break channels
On-Chip Oscillation Circuits:
• Clock source selectable between an external supply (EXTAL or CKIO) and crystal resonator
• Three types of clocks generated:
8-/16-/32-bit access from the CPU
Maximum two 16-bit accesses from the DSP
8-/16-/32-bit access from the DMAC or E-DMAC
The internal clock and peripheral clock can be adjusted by setting the PLL circuit and division
ratio.
CPU clock (I clock): 200 MHz (max)
Bus clock (B clock): 66 MHz (max)
Peripheral clock (P clock): 33 MHz (max)
Rev. 1.00 Dec. 27, 2005 Page 3 of 932
Section 1 Overview and Pin Function
REJ09B0269-0100

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