HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 137

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.4
In DSP mode, data transfer instructions are added for the DSP unit registers. The newly added
instructions are classified into the following three groups.
1. Double data transfer instructions
2. Single data transfer instructions
3. System control instructions
In any DSP data transfer instructions, an address to be accessed is generated and output by the
CPU. For DSP data transfer instructions, some of the CPU general registers are used for address
generation and specific addressing modes are used.
The DSP unit is connected to the X memory and Y memory via the specific buses called X bus
and Y bus. By using the data transfer instructions using the X and Y buses, two data items can
be transferred between the DSP unit and X/Y memories simultaneously. These instructions are
called double data transfer instructions. These double data transfer instructions can be
described in combination with the DSP operation instructions to execute data transfer and data
operation in parallel,
The DSP unit is also connected to the L bus that is used by the CPU. The DSP registers other
than the DSR can access any logical addresses generated by the CPU. In this case, the single
data transfer instructions are used. The single data transfer instructions cannot be used in
combination with the DSP operation instructions and can access only one data item at a time.
Some of the DSP unit registers are handled as the CPU system registers. To control these
system registers, the system control registers are supported. The DSP registers are connected to
the CPU general registers via the data transfer bus (C bus).
DSP Data Transfer Instructions
Rev. 1.00 Dec. 27, 2005 Page 93 of 1044
Section 3 DSP Operating Unit
REJ09B0269-0100