HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 331

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.3.7
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
9.3.8
Break Condition Specified for L Bus Instruction Fetch Cycle:
• Register specifications
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
 If a branch occurs due to a branch instruction, the address of the branch instruction is saved
 If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception
When a repeat loop of the DSP extended function is used, control being transferred from the
repeat end instruction to the repeat start instruction is not recognized as a branch, and the
values are not stored in BRSR and BRDR.
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the
PCTE bit (in BRCR) off and on, the values in the queues are invalid.
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not
The ASID check is not included.
<Channel B>
Address:
Data:
in BRSR and the address of the branch destination instruction is saved in BRDR.
occurrence is saved in BRSR and the start address of the exception handling routine is
saved in BRDR.
PC Trace
Usage Examples
H'00000404, Address mask: H'00000000
included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
Rev. 1.00 Dec. 27, 2005 Page 287 of 932
Section 9 User Break Controller
REJ09B0269-0100