DV164136 Microchip Technology, DV164136 Datasheet - Page 50

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the LP, XT,
TABLE 3-2:
DS39646C-page 48
Note 1:
is not stopped and
HS or HSPLL modes.
Primary Device Clock
2:
3:
4:
(PRI_IDLE mode)
T1OSC or INTRC
before Wake-up
Clock Source
(Sleep mode)
INTOSC
T
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies. On Reset, INTOSC defaults
to 1 MHz.
T
(parameter F12, Table 28-7); it is also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
(parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
is the Oscillator Start-up Timer (parameter 32, Table 28-12). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(2)
IOBST
after Wake-up
Clock Source
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(parameter 39, Table 28-12), the INTOSC stabilization period.
(2)
(2)
(2)
(2)
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
PLL
.
following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST
None
CSD
CSD
CSD
CSD
OST
OST
OST
rc
+ t
+ t
+ t
is the PLL Lock-out Timer
(1)
(3)
(1)
(4)
(1)
(3)
(1)
rc
(4)
rc
rc
(4)
(3)
(3)
(3)
© 2008 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS