DV164136 Microchip Technology, DV164136 Datasheet - Page 270

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Synchronous Master mode in that the shift clock is
PIC18F8722 FAMILY
20.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
supplied externally at the CKx pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any low-power
mode.
20.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 20-9:
DS39646C-page 268
INTCON
PIR1
PIE1
IPR1
TRISC
TRISG
RCSTAx
TXREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSRx register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of
TSRx, the TXREGx register will transfer the
second word to the TSRx and flag bit, TXxIF, will
now be set.
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSARTx Transmit Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
TRISC7
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
TRISC6
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
—
TRISC5
RC1IE
RC1IP
RC1IF
SREN
TXEN
Bit 5
—
—
TRISC4
TRISG4
INT0IE
TX1IE
TX1IP
CREN
SYNC
TX1IF
SCKP
Bit 4
TRISG3
SSP1IE
SSP1IP
TRISC3
ADDEN
SSP1IF
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IE
CCP1IP
TRISG2
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
TRISC1
TRISG1
INT0IF
OERR
TRMT
WUE
Bit 1
© 2008 Microchip Technology Inc.
TMR1IE
TMR1IP
TRISG0
TMR1IF
TRISC0
ABDEN
RX9D
TX9D
RBIF
Bit 0
on page
Values
Reset
57
60
60
60
60
60
59
59
59
61
61
59