DV164136 Microchip Technology, DV164136 Datasheet - Page 198

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
18.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin
(Figure 18-4). This mode can be used for half-bridge
applications, as shown in Figure 18-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
P1DC<6:0> sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 18.4.6
“Programmable Dead-Band Delay” for more details
on dead-band delay operations.
FIGURE 18-5:
DS39646C-page 196
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
PIC18F6X27/6X22/8X27/8X22
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18F6X27/6X22/8X27/8X22
P1A
P1B
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
The P1A and P1B outputs are multiplexed with the
PORTC<2> and PORTE<6> data latches. Alternatively,
P1B can be assigned to PORTH<7> by programming
the ECCPMX Configuration bit to ‘0’. See Table 18-1,
Table 18-2 and Table 18-3 for more information. The
associated TRIS bit must be cleared to configure P1A
and P1B as outputs.
FIGURE 18-4:
Note 1: At this time, the TMR2 register is equal to the
P1A
P1B
td = Dead Band Delay
(2)
(2)
2: Output signals are shown as active-high.
Load
V+
V-
(1)
PR2 register.
V+
V-
td
Duty Cycle
Period
Load
td
HALF-BRIDGE PWM
OUTPUT
© 2008 Microchip Technology Inc.
FET
Driver
FET
Driver
(1)
+
V
-
+
V
-
Period
(1)