DV164136 Microchip Technology, DV164136 Datasheet - Page 344

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
DS39646C-page 342
Q Cycle Activity:
After Instruction
operation
Decode
PC =
No
Q1
Read literal
Address (THERE)
operation
‘k’<7:0>,
Unconditional Branch
GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTO is always a two-cycle
instruction.
2
2
GOTO THERE
1110
1111
No
Q2
k19kkk
1111
operation
operation
No
No
Q3
k7kkk
kkkk
Read literal
Write to PC
‘k’<19:8>,
operation
No
Q4
kkkk0
kkkk8
INCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
C
DC
CNT
Z
C
DC
Q1
=
=
=
=
=
=
=
=
register ‘f’
Increment f
INCF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
INCF
C, DC, N, OV, Z
Read
0010
Q2
FFh
0
?
?
00h
1
1
1
© 2008 Microchip Technology Inc.
f {,d {,a}}
10da
CNT, 1, 0
Process
Data
Q3
ffff
destination
Write to
Q4
ffff