DV164136 Microchip Technology, DV164136 Datasheet - Page 402
![DEVELOPMENT KIT FOR PIC18](/photos/9/21/92129/dv164136_sml.jpg)
DV164136
Manufacturer Part Number
DV164136
Description
DEVELOPMENT KIT FOR PIC18
Manufacturer
Microchip Technology
Series
PIC®r
Type
MCUr
Datasheets
1.DM183032.pdf
(38 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(6 pages)
4.DV164136.pdf
(446 pages)
5.DV164136.pdf
(4 pages)
6.DV164136.pdf
(18 pages)
Specifications of DV164136
Contents
Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
Processor To Be Evaluated
PIC18F8722, PIC18F87J11
Interface Type
RS-232, USB
Operating Supply Voltage
3.3 V, 5 V
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18F8xxx
Kit Contents
PIC18 Exp Brd PICkit 3 Cable CD PSU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PIC18F8722, PIC18F87J11
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DV164136
Manufacturer:
MICROCHIP
Quantity:
12 000
- DM183032 PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- DV164136 PDF datasheet #4
- DV164136 PDF datasheet #5
- DV164136 PDF datasheet #6
- Current page: 402 of 446
- Download datasheet (7Mb)
PIC18F8722 FAMILY
FIGURE 28-7:
TABLE 28-9:
DS39646C-page 400
10
11
12
13
14
15
16
17
18
18A
19
20
20A
21
21A
22†
23†
Note 1:
Param
No.
(Output)
I/O pin
I/O pin
(Input)
OSC1
CLKO
Note:
† These parameters are asynchronous events not related to any internal clock edges.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OS
OS
CK
CK
CK
CK
OS
OS
Symbol
IO
IO
IO
IO
INP
RBP
Measurements are taken in RC mode, where CLKO output is 4 x T
V2
V2
R
F
H2
R
F
L2
H2
H2
H2
H2
CK
OS
IO
CK
IO
CK
IO
IO
Refer to Figure 28-5 for load conditions.
V CLKO ↓ to Port Out Valid
H Port In Valid before CLKO ↑
I
V OSC1 ↑ (Q1 cycle) to Port Out Valid
I
H Port Input Valid to OSC1 ↑ (I/O in setup
H OSC1 ↑ to CLKO ↑
L OSC1 ↑ to CLKO ↓
CLKO AND I/O TIMING REQUIREMENTS
CLKO Rise Time
CLKO Fall Time
Port In Hold after CLKO ↑
OSC1 ↑ (Q2 cycle) to
Port Input Invalid
(I/O in hold time)
time)
Port Output Rise Time
Port Output Fall Time
INTx pin High or Low Time
RB<7:4> Change INTx High or Low Time
CLKO AND I/O TIMING
Old Value
Q4
Characteristic
10
13
17
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
14
20, 21
Q1
19
0.25 T
18
Min
100
200
T
T
—
—
—
—
—
—
—
—
—
—
CY
0
0
CY
CY
+ 25
Q2
15
OSC
New Value
Typ
75
75
35
35
—
—
—
50
—
—
—
10
10
—
—
—
—
.
0.5 T
© 2008 Microchip Technology Inc.
Max
200
200
100
100
150
CY
25
60
25
60
—
—
—
—
—
—
—
11
12
+ 20
16
Units Conditions
Q3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
DD
DD
DD
= 2.0V
= 2.0V
= 2.0V
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