Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 121

• Manufacturer Part Number: Z8F64220100ZDA
• Description: ADAPTER ICE Z8 ENCORE 64K 64LQFP
• Manufacturer: Zilog

Specifications of Z8F64220100ZDA

• Module/board Type: *
• For Use With/related Products: Z8 Encore!™
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3403

PS019921-0308
DE
1
0
1
0
Idle State
Figure 16. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
of Line
UART Interrupts
when a byte is written to the UART Transmit Data register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This timing allows a setup time to enable the transceiver. The
Driver Enable signal deasserts one system clock period after the last Stop bit is transmit-
ted. This one system clock delay allows both time for data to clear the transceiver before
disabling it, as well as the ability to determine if another character follows the current
character. In the event of back to back characters (new data must be written to the Trans-
mit Data Register before the previous character is completely transmitted) the
not deasserted between characters. The
polarity of the Driver Enable signal.
The Driver Enable to Start bit setup time is calculated as follows:
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(
mission. The
of data out. At this point, the Transmit Data register may be written with the next character
to send. This provides 7 bit periods of latency to load the Transmit Data register before the
Transmit shift register completes shifting the current character. Writing to the UART
Transmit Data register clears the
Start
TDRE


------------------------------------ -
Baud Rate (Hz)
) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
Bit0
lsb
1
TDRE
Bit1
interrupt occurs after the Transmit shift register has shifted the first bit


≤
DE to Start Bit Setup Time (s)
Bit2
Bit3
Data Field
TDRE
Bit4
bit to 0.
DEPOL
Bit5
bit in the UART Control Register 1 sets the
≤
Bit6


------------------------------------ -
Baud Rate (Hz)
Z8 Encore! XP
msb
Bit7
2
Product Specification
Parity


®
Stop Bit
F64XX Series
1
DE
signal is
UART
107