Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 149

• Manufacturer Part Number: Z8F64220100ZDA
• Description: ADAPTER ICE Z8 ENCORE 64K 64LQFP
• Manufacturer: Zilog

Specifications of Z8F64220100ZDA

• Module/board Type: *
• For Use With/related Products: Z8 Encore!™
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3403

Table 65. SPI Status Register (SPISTAT)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
SPI Status Register
IRQ
7
The SPI Status register
their reset state if the SPIEN bit in the SPICTL register = 0.
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
pleted.
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved—Must be 0.
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave,
OVR
6
R/W*
COL
5
(Table
65) indicates the current state of the SPI. All bits revert to
ABT
4
0
F62H
3
Reserved
Z8 Encore! XP
2
Product Specification
R
Serial Peripheral Interface
TXST
1
®
F64XX Series
SLAS
0
1
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