Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 160

• Manufacturer Part Number: Z8F64220100ZDA
• Description: ADAPTER ICE Z8 ENCORE 64K 64LQFP
• Manufacturer: Zilog

Specifications of Z8F64220100ZDA

• Module/board Type: *
• For Use With/related Products: Z8 Encore!™
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3403

PS019921-0308
Address Only Transaction with a 10-bit Address
13. The I
14. If more bytes remain to be sent, return to
15. Software responds by setting the STOP bit of the I
16. The I
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
18. The I
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction can be done which only con-
sists of an address phase.
a slave with 10-bit address will acknowledge. As an example, this transaction can be used
after a ‘write’ has been done to a EEPROM to determine when the EEPROM completes its
internal write operation and is once again responding to I
not Acknowledge the transaction can be repeated until the slave is able to Acknowledge.
Follow the steps below for an address only transaction to a 10-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
5. Software asserts the START bit of the I
6. The I
S
sent, the Transmit interrupt is asserted.
to initiate a new transaction). In the STOP case, software clears the TXI bit of the I
Control register at the same time.
the STOP or START bit is already set, the NCKI interrupt does not occur.
STOP or START bit is cleared.
least-significant bit must be 0 for the write operation.
Slave Address
Figure 29. 10-Bit Address Only Transaction Format
1st 7 bits
2
2
2
2
2
C Controller shifts the data out of using the SDA signal. After the first bit is
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP (or RESTART) condition to the I
C interrupt asserts, because the I
C Controller sends the START condition to the I
W = 0 A/A
Figure 29
displays this ‘address only’ transaction to determine if
2
2
C Control register.
C Control register to enable Transmit interrupts.
2
2
Slave Address
C Data register is empty (TDRE = 1)
C Control register.
step
2nd Byte
9.
2
Z8 Encore! XP
C Control register (or START bit
2
C transactions. If the slave does
2
C slave.
Product Specification
A/A P
®
2
C bus. The
F64XX Series
I2C Controller
2
C
146