APMOTOR56F8000E Freescale Semiconductor, APMOTOR56F8000E Datasheet - Page 29

• Manufacturer Part Number: APMOTOR56F8000E
• Description: KIT DEMO MOTOR CTRL SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: Motor / Motion Controllers & Driversr

Specifications of APMOTOR56F8000E

• Accessory Type: Motor Controller
• Input Voltage: 9 V
• Interface Type: RS-232
• Product: Power Management Modules
• For Use With/related Products: DEMO56F8013, DEMO56F8013-E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5 Pin Descriptions
3.5.1
After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has
the option of switching to an external clock reference by enabling the PRECS bit in the OCCS Oscillator
Control register, if desired.
Part 4 Memory Map
4.1 Introduction
The 56F8014 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style
architecture with two independent memory spaces for Data and Program. On-chip RAM is used in both
spaces and Flash memory is used only in Program space.
This section provides memory maps for:
On-chip memory sizes for the device are summarized in
identified in the “Use Restrictions” column of
4.2 Interrupt Vector Table
Table 4-2
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.
As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see
for the reset value of the VBA.
By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt
vector table. In these instances, the first two locations in the vector table must contain branch or JMP
instructions. All other entries must contain JSR instructions.
Freescale Semiconductor
•
•
Program Flash
(PFLASH)
Unified RAM (ram)
On-Chip Memory
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
provides the 56F8014’s reset and interrupt priority structure, including on-chip peripherals. The
External Reference (GPIOB6 / RXD / SDA / CLKIN)
56F8014
8k x 16
2k x 16
Table 4-1 Chip Memory Configurations
Erase / Program via Flash interface unit and word writes to CDBW
Usable by both the Program and Data memory spaces
56F8014 Technical Data, Rev. 11
Table
4-1.
Table
Use Restrictions
4-1. Flash memories’ restrictions are
Section 5.5.6
Pin Descriptions
29