MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 53

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
15.
16. The maximum limit for this parameter is not a device limit. The device will operate
17. This is not a device limit. The device will operate with a negative value, but system
18. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
19. MIN (
20. The refresh period equals 64ms. This equates to an average refresh rate of 15.625µs.
21. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
22. The valid data window is derived by achieving other specifications:
23. Referenced to each output group: LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
25. To maintain a valid level, the transitioning edge of the input must:
26. The input capacitance per ball group will not differ by more than this maximum
27. CK and CK# input slew rate must be ≥ 1V/ns (2V/ns if measured differentially).
28. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the
29.
30. READs and WRITEs with auto precharge are not allowed to be issued until
31. Any positive glitch must be less than 1/3 of the clock cycle and not more than +200mV
32.
t
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
with a greater value for this parameter, but system performance (bus turnaround) will
degrade accordingly.
performance could be degraded due to bus turnaround.
command.
the minimum absolute value for the respective parameter.
surements is the largest multiple of
t
maximum amount for any given device.
t
with the clock duty cycle and a practical data valid window can be derived. The clock
is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio.
during REFRESH command period (
standby).
amount for any given device.
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps (pending)
must be added to
exceeds 4V/ns, functionality is uncertain.
t
device CK and CK# inputs, collectively.
can be satisfied prior to the internal PRECHARGE command being issued.
or 2.0V (pending), whichever is less. Any negative glitch must be less than 1/3 of the
clock cycle and not exceed either -150mV or 1.6V (pending), whichever is more posi-
tive.
The voltage levels used are derived from a minimum
test load. In practice, the voltage levels obtained from a properly terminated bus
will provide significantly different voltage values.
HZ and
RAS.
DQSQ, and
HP (MIN) is the lesser of
a. Sustain a constant slew rate from the current AC level through to the target AC
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, V
level, V
t
RC or
t
LZ transitions occur in the same access time windows as valid data transi-
IL
t
t
IL
(
QH (
RFC) for I
AC
(
DC
), or V
) or V
t
t
HP -
DS and
IH
DD
IH
t
(
QHS). The data valid window derates directly proportional
AC
(
t
DC
measurements is the smallest multiple of
CL minimum and
t
53
).
DH for each 100mv/ns reduction in slew rate. If slew rate
).
128Mb: 8 Meg x 16 Mobile DDR SDRAM
t
CK that meets the maximum absolute value for
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC [MIN]) else CKE is LOW (i.e., during
t
CH minimum actually applied to the
V
DD
t
RAS (MAX) for I
©2006 Micron Technology, Inc. All rights reserved.
level and the referenced
t
t
HP (
CK that meets
t
CK/2),
t
RAS (MIN)
DD
Advance
Notes
mea-