MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 15

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 7:
Table 8:
PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank)
or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER (standard or extended mode
registers)
Name (Function)
Write enable
Write inhibit
Truth Table – Commands
Notes 1 and 11 apply to all commands
Truth Table – DM Operation
Notes:
Name (Function)
Note:
10. This command is a BURST TERMINATE if CKE is HIGH.
11. All states and sequences not shown are reserved and/or illegal.
2. BA0–BA1 select either the standard mode register or the extended mode register
3. BA0–BA1 provide bank address and A0–A11 provide row address.
4. BA0–BA1 provide bank address; A0–A8 provide column address; A10 HIGH enables the auto
5.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and
9. DESELECT and NOP are functionally interchangeable.
Table 7 and Table 8 provide quick references of available commands. This is followed by
a written description of each command. Three additional Truth Tables (Table 9 on
page 42, Table 10 on page 43, and Table 11 on page 45) provide CKE commands and
current/next state information.
1. CKE is HIGH for all commands shown except SELF REFRESH.
(BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 1, BA1 = 0 select extended mode
register; other combinations of BA0–BA1 are reserved). A0–A11 provide the op-code to be
written to the selected mode register.
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0
for CKE.
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
Used to mask write data; provided coincident with corresponding data.
15
CS#
H
L
L
L
L
L
L
L
L
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
X
H
H
H
H
L
L
L
L
–
BA1 are “Don’t Care.”
CAS#
X
H
H
H
H
L
L
L
L
DM
H
L
WE#
X
H
H
H
H
L
L
L
L
©2006 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
Commands
Valid
DQ
X
Advance
Notes
8, 10
6, 7
9
9
3
4
4
5
2