MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 46

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
3b. The minimum delay from a READ or WRITE command with auto precharge
CL
BL = Bust length
are idle.
represented by the current state only.
precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a
WRITE command.
t
period starts with registration of the command and ends where the precharge
period (or
This device supports concurrent auto precharge such that when a read with
auto precharge enabled or a write with auto precharge is enabled any com-
mand to other banks is allowed, long as that command does not interrupt the
read or write data transfer already in process. either case, all other related lim-
itations apply (e.g., contention between read data and write data must be
avoided).
enabled, to a command to a different bank is summarized below.
WR ends, with
RU
= CAS latency (CL) rounded up to the next integer
From Command
WRITE w/AP
READ w/AP
t
RP) begins.
t
WR measured as if auto precharge was disabled. The access
46
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
To Command
©2006 Micron Technology, Inc. All rights reserved.
(with Concurrent Auto
[1 + (BL/2)]
[CL
Minimum Delay
Precharge)
RU
(BL/2) ×
(BL/2)
+ (BL/2)]
1
1
1
1
Truth Tables
t
t
t
t
CK
CK
CK
CK
t
CK +
t
CK
t
CK
t
t
Advance
CK
WTR