MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 12

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4:
Operating Mode
Extended Mode Register
Temperature-Compensated Self Refresh (TCSR)
PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
CAS Latency
Notes:
2. Shown with nominal
COMMAND
COMMAND
1. BL = 4 in the cases shown.
The normal operating mode is selected by issuing a LOAD MODE REGISTER SET
command with bits A7–A11 each set to zero, and bits A0–A6 set to the desired values.
All other combinations of values for A7–A11 are reserved for future use and/or test
modes. Test modes and reserved states should not be used because unknown operation
or incompatibility with future versions may result.
The extended mode register controls functions specific to low power operation. These
additional functions include drive strength, temperature-compensated self refresh
(TCSR), and PASR.
This device has default values for the extended mode register (if not programmed, the
device will operate with the default values – PASR = Full Array, DS = Full Drive).
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator on the device. Programming of the TCSR
bits will have no effect on the device. The self refresh oscillator will continue refresh at
the factory programmed optimal rate for the device temperature.
CK#
DQS
CK#
DQS
DQ
DQ
CK
CK
READ
READ
T0
T0
1n clock
t
AC and nominal
CL = 2
2n clock
NOP
NOP
T1
T1
CL = 3
12
t
TRANSITIONING DATA
AC
T1n
128Mb: 8 Meg x 16 Mobile DDR SDRAM
D
OUT
T2
NOP
n
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
T2
DSDQ.
t
AC
T2n
D
n + 1
T2n
OUT
D
D
n + 2
T3
OUT
NOP
n
OUT
NOP
T3
DON’T CARE
T3n
D
n + 3
D
n + 1
T3n
OUT
OUT
©2006 Micron Technology, Inc. All rights reserved.
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