H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 270

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
12.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 12.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Clocked synchronous mode
Legend:
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0
n: Determined by the SMR settings shown in the following table.
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate settable for each frequency. Table 12.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 12.5 and 12.7 show the maximum bit rates with external clock
input.
Rev. 2.00 Mar 21, 2006 page 232 of 518
REJ09B0299-0200
: Operating frequency (MHz)
CKS1
0
0
1
1
Bit Rate Register (BRR)
SMR Setting
CKS0
0
1
0
1
Bit Rate
B =
B =
n
0
1
2
3
64
64
2
2
φ
φ
2n-1
2n-1
N
10
10
6
(N+1)
6
(N+1)
255)
Error
Error (%) = {
—
B
64
φ
2
10
2n-1
6
(N+1)
- 1 }
100