H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 232
H8S2110B
Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S2110B.pdf
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Section 10 8-Bit Timer (TMR)
10.5.2
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
match, the compare-match signal is not generated until the next TCNT input clock. Figure 10.6
shows the timing of CMF flag setting.
10.5.3
When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0
bits in TCSR. Figure 10.7 shows the timing of timer output when the output is set to toggle by a
compare-match A signal.
Rev. 2.00 Mar 21, 2006 page 194 of 518
REJ09B0299-0200
Compare-match A
signal
Timer output pin
Figure 10.7 Timing of Toggled Timer Output by Compare-Match A Signal
Timing of CMFA and CMFB Setting at Compare-Match
Timing of Timer Output at Compare-Match
Compare-match
signal
CMF
TCNT
TCOR
Figure 10.6 Timing of CMF Setting at Compare-Match
N
N
N + 1
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