H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 220
H8S2110B
Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S2110B.pdf
(559 pages)
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Section 10 8-Bit Timer (TMR)
Channel CKS2
Common 1
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is
Table 10.2 Clock Input to TCNT and Count Condition (2)
Channel CKS2
TMR_Y
Rev. 2.00 Mar 21, 2006 page 182 of 518
REJ09B0299-0200
set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be
generated. These settings should not be made.
TCR
1
1
TCR
0
0
0
0
1
0
0
0
0
1
1
1
1
CKS1
0
1
1
CKS1
0
0
1
1
0
0
0
1
1
0
0
1
1
CKS0
1
0
1
CKS0
0
1
0
1
0
0
1
0
1
0
1
0
1
STCR
ICKS1
—
—
—
TCRXY *
CKSX
—
—
—
—
—
—
—
—
—
—
—
—
—
2
ICKS0
—
—
—
CKSY
0
0
0
0
0
1
1
1
1
1
—
—
—
Description
Increments at rising edge of external
clock
Increments at falling edge of external
clock
Increments at both rising and falling
edges of external clock
Description
Disables clock input
Increments at /4
Increments at /256
Increments at /2048
Disables clock input
Disables clock input
Increments at /4096
Increments at /8192
Increments at /16384
Increments at overflow signal from
TCNT_X *
Increments at rising edge of external
clock
Increments at falling edge of external
clock
Increments at both rising and falling
edges of external clock
1
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