PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 92
PC87332VLJ-5
Manufacturer Part Number
PC87332VLJ-5
Description
PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
Manufacturer
NSC [National Semiconductor]
Datasheet
1.PC87332VLJ-5.pdf
(98 pages)
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Symbol
t
t
t
t
t
t
t
t
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t
9 0 Electrical Characteristics
9 3 8 DMA Timing
Note 1 For FDC DMA Values shown are with the FIFO disabled or with FIFO enabled and THRESH
Note 2 The active edge of RD or WR and TC is recognized only when FDACK or PDACK is active
KI
KK
KQ
QK
QP
QQ
QR
QW
QT
RQ
TQ
TT
t
For ECP DMA Value shown is with the FIFO disabled For FIFO enabled add (192
DRP
) to the values shown
FDACK or PDACK Inactive Pulse Width
FDACK or PDACK Active Pulse Width
FDACK Active Edge to FDRQ Inactive (Note 1)
PDACK Active Edge to PDRQ Inactive (Note 1)
FDRQ to FDACK Active Edge
PDRQ to PDACK Active Edge
FDRQ Period (FDC-Burst DMA)
PDRQ Period (ECP)
FDRQ or PDRQ Inactive Non-Burst Pulse Width
FDRQ to RD or WR Active
PDRQ to RD or WR Active
FDRQ to End of RD WR (Note 1)
(FDRQ Service Time)
FDRQ to TC Active (Note 1)
(FDRQ Service Time)
RD WR Active Edge to FDRQ or PDRQ Inactive (Note 2)
TC Active Edge to FDRQ or PDRQ Inactive
TC Active Pulse Width
Parameter
(Continued)
FIGURE 9-8 DMA Timing
92
c
T
8
CP
c
) to the value shown (assuming IOCHRDY
Min
330
300
25
65
10
15
50
e
t
DRP
0 For non-zero values of THRESH add (THRESH
(8
(8
c
c
t
t
DRP
DRP
)
)
Max
400
65
b
b
65
75
(16
(16
c
c
t
t
ICP
ICP
e
TL C 11930 – 33
)
)
1)
Units
c
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
s
s
s
s
c
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