PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 72

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

A2
0
0
0
0
1
1
1
1
7 0 Parallel Port
The software must write zero to bits 0 1 and 3 of the CTR
register before accessing the EPP registers since the pins
controlled by these bits are controlled by hardware during
EPP access Once these bits are written with zero the soft-
ware may issue multiple EPP access cycles The software
must set bit 7 of the PTR register to 1 if bit 5 of CTR is to
control direction
To meet the EPP 1 9 specifications the software should
change direction (bit 5 of CTR) only when bit 7 of STR is 1
(i e change direction at EPP Idle Phase as defined in the
IEEE 1284 document)
When bit 7 of PTR is 0 EPP cycles to the external device
are generated by invoking read or write cycles to the EPP
When bit 7 of PTR is 1
1 Reading an EPP register during forward direction (bit 5 of
2 Writing to an EPP register during backward direction (bit
EPP 1 7 Address Write
The following procedure selects a peripheral device or reg-
ister See also Figure 7-1
1 The host writes a byte to the EPP address register WR
2 The EPP pulls ASTRB low to indicate that data has been
CTR is 0) is allowed only in EPP 1 7 It returns the regis-
ter latched value (not the PD0–7 pins’ value) and does
not generate an EPP read cycle
5 of CTR is 1) updates the register data and does not
generate an EPP write cycle
goes low to latch D0–7 into the address register The
latch drives the address register onto PD0–7 and the
EPP pulls WRITE low
sent
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Address
0
1
2
3
4
5
6
7
Control (CTR)
Status (STR)
(Continued)
Data (DTR)
Data Port 0
Data Port 1
Data Port 2
Data Port 3
Register
Address
Access
R W
R W
R W
R W
R W
R W
R W
TABLE 7-5 EPP Register Addresses
R
A write to this register sets the state of the eight data pins on the 25-pin
D-shell connector
A read from this register presents the system micro-processor with the real-
time status of five pins on the 25-pin D-shell connector and the IRQ
A write operation to this register sets the state of four pins on the 25-pin
D-shell connector and controls both the parallel port interrupt enable and
direction
A write operation to this register initiates an EPP device register selection
operation
Accesses to this port initiate device read or write operations with bits 0 – 7
This port is only accessed to transfer bits 8 to 15 of a 16-bit read or write to
data port 0
This port is only accessed to transfer bits 16 to 23 of a 32-bit read or write to
data port 0
This port is only accessed to transfer bits 24 to 31 of a 32-bit read or write to
data port 0
72
3 If WAIT is low during the host write cycle IOCHRDY
4 When IOCHRDY goes high it causes WR to go high If
5 When WR goes high it causes the EPP to pull WRITE
goes low
When WAIT goes high the EPP pulls IOCHRDY high
WAIT is high during the host write cycle then the EPP
does not pull IOCHRDY to low
and ASTRB to high
Only when WRITE and ASTRB are high can the EPP
change PD0– 7
FIGURE 7-1 EPP 1 7 Address Write
Description
TL C 11930 – 15