PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 78

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

7 0 Parallel Port
The FIFO does not stall when overwritten or underrun (ac-
cess is ignored) Bytes are always read from the top of the
FIFO regardless of the direction bit (bit 5 of DCR) For ex-
ample if 44h 33h 22h 11h are written into the FIFO read-
ing the FIFO returns 44h 33h 22h 11h (in the same order it
was written)
CNFGA Configuration Register A Read only Reading this
register always returns 00010000 Writing this register has
no effect and the data is ignored
CNFGB Configuration Register B Read only Reading this
register returns the configuration parallel port interrupt line
and its state as follows
Bit 7
Bit 6
Bits 5 4 These bits are 1 when IRQ5 is configured and 0
Bit 3
Bits 2
1 0
ECR
Bit 7
6 5
Bit 4
This bit is always 0
Holds the (non-inverted) value on the configured
IRQ pin
when IRQ7 is configured
This bit is always 1
These bits are always 0 Writing to this register
has no effect and the data is ignored
Extended Control Register This register controls
the ECP and parallel port functions On reset this
register is initialized to 00010101 IOCHRDY is
driven low on an ECR read when the ECR status
bits do not hold updated data
These three bits determine the mode of operation
(Mode) Bit 7 is the MSB
000 Standard mode Write cycles are performed
001 PS 2 mode Read and write cycles are per-
010 Parallel Port FIFO mode Write cycles are
011 ECP FIFO mode The FIFO direction is con-
100 Reserved
101 Reserved
110 FIFO test mode The FIFO is accessible via
111 Configuration
ECP Interrupt Mask bit When this bit is 0 an inter-
rupt is generated on ERR assertion (the high-to-
low edge of ERR) An interrupt is also generated
when ERR is asserted while this bit is changed
under software control
Bit 5 of DCR is forced to 0 (forward direction)
and PD0–7 is driven The FIFO is reset (emp-
ty)
formed under software control The FIFO is
reset (empty)
performed under hardware control (STB is
controlled by hardware) Bit 5 of DCR is
forced to 0 (forward direction) and PD0–7
are driven
trolled by bit 5 of DCR
Read and write cycles to the device are per-
formed under hardware control (STB and
AFD are controlled by hardware)
the TFIFO register
The ECP does not issue ECP cycles to fill
empty the FIFO
CNFGB registers are accessible in this
mode
(Continued)
mode
The
CNFGA
and
78
Bit 3
Bit 2
Bit 1
Bit 0
7 8 SOFTWARE CONTROLLED DATA TRANSFER
(Modes 000 and 001)
Software controlled data transfer is supported in modes 000
and 001 The software generates peripheral-device cycles
by modifying the DATAR and DCR registers and reading the
DSR DCR and DATAR registers The negotiation phase
and nibble mode transfer as defined in the IEEE 1284 stan-
dard are performed in these modes
In these modes the FIFO is reset (empty) and is not func-
tional The DMA and RLE are idle
Mode 000 is for the forward direction only the direction bit
is forced to 0 and PD0– 7 is driven Mode 001 is for both the
forward and backward directions The direction bit controls
whether PD0 – 7 are driven
from 1 to 0 this prevents the loss of an interrupt
between an ECR read and ECR write When this
bit is 1 no interrupt is generated
ECP DMA Enable bit When this bit is 0 DMA is
disabled and the PDRQ pin is in TRI-STATE
When this bit is 1 DMA is enabled and DMA starts
when bit 2 of ECR is 0
Note PDACK is assumed inactive when this bit is 0
ECP Service bit When this bit is 0 and one of the
following three interrupt events occur an interrupt
is generated and this bit is set to 1 by hardware
1 Bit 3 of ECR is 1 and terminal count is reached
during DMA
2 Bit 3 of ECR is 0 and bit 5 of DCR is 0 and
there are eight or more bytes free in the FIFO
3 Bit 3 of ECR is 0 and bit 5 of DCR is 1 and
there are eight or more bytes to be read from the
FIFO
When this bit is 1 DMA and the above three inter-
rupts are disabled
Writing 1 to this bit does not cause an interrupt
When the ECP clock is frozen this bit is read as 0
regardless of its actual value (even though the bit
may be modified by software when the ECP clock
is frozen)
FIFO Full bit Read only
This bit is 0 when the FIFO has at least one free
byte
This bit is 1 when the FIFO is full
This bit continuously reflects the FIFO state and
therefore can only be read Data written to this bit
is ignored
When the ECP clock is frozen this bit is read as 1
regardless of the actual FIFO state
FIFO Empty bit Read only
This bit is 0 when the FIFO has at least one byte
of data
This bit is 1 when the FIFO is empty
This bit continuously reflects the FIFO state and
therefore can only be read Data written to this bit
is ignored
When the ECP clock is frozen this bit is read as 1
regardless of the actual FIFO state