PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 67

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

6 0 Serial Ports
6 4 LINE STATUS REGISTER (LSR)
This 8-bit register provides status information to the CPU
concerning data transfers Table 6-2 shows the contents of
the Line Status Register Details on each bit follow
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
This bit is the receiver Data Ready (DR) indicator It
is set to 1 whenever a complete incoming character
has been received and transferred into the Receiver
Buffer Register or the FIFO It is reset to 0 by read-
ing the data in the Receiver Buffer Register or the
FIFO
This bit is the Overrun Error (OE) indicator It indi-
cates that data in the Receiver Buffer Register was
not read by the CPU before the next character was
transferred into the Receiver Buffer Register there-
by destroying the previous character The OE indica-
tor is set to 1 upon detection of an overrun condition
and reset whenever the CPU reads the contents of
the Line Status Register If the FIFO mode data con-
tinues to fill the FIFO beyond the trigger level an
Overrun error will occur only after the FIFO is com-
pletely full and the next character has been received
in the shift register OE is indicated to the CPU as
soon as it happens The character in the shift regis-
ter is overwritten but it is not transferred to the
FIFO
This bit is the Parity Error (PE) indicator It indicates
that the received data character does not have the
correct parity as selected by the even parity select
bit The PE bit is set to 1 upon detection of a parity
error and is reset to 0 whenever the CPU reads the
contents of the Line Status Register In the FIFO
mode this error is associated with the particular
character that it applies to in the FIFO This error is
revealed to the CPU when its associated character is
at the top of the FIFO
This bit is the Framing Error (FE) indicator It indi-
cates that the received character did not have a val-
id Stop bit It is set to 1 whenever the Stop bit follow-
ing the last data bit or parity bit is a 0 (Spacing level)
The FE indicator is reset whenever the CPU reads
the contents of the Line Status Register In the FIFO
mode this error is associated with the particular
character that it applies to in the FIFO This error is
revealed to the CPU when its associated character is
at the top of the FIFO The UART will try to resyn-
chronize after a framing error by assuming that the
error was due to the next start bit It samples this
‘‘start’’ bit twice and then takes in the bits following it
as the rest of the frame
This bit is the Break Interrupt (BI) indicator It is set
to 1 whenever the received data input is held in the
Spacing (0) state for longer than a full word trans-
mission time (i e the total time of Start bit
bits
whenever the CPU reads the contents of the Line
Status Register In the FIFO mode this error is asso-
ciated with the particular character that it applies to
in the FIFO This error is revealed to the CPU when
its associated character is at the top of the FIFO
a
Parity
a
Stop bits) The BI indicator is reset
(Continued)
a
data
67
Bit 5
Bit 6
Bit 7
6 5 FIFO CONTROL REGISTER (FCR)
This is a write-only register at the same location as the IIR
(the IIR is a read-only register) This register is used to en-
able the FIFOs clear the FIFOs and to set the RCVR FIFO
trigger level
Bit 0
Bit 1
Bit 2
Bit 3
Bits 4 5 FCR4 to FCR5 are reserved for future use
When a break occurs only one character is loaded
into the FIFO To Restart after a break is received
the SIN pin must be 1 for at least one half bit time
Note Bits 1 through 4 are the error conditions that produce a
This bit is the Transmitter Holding Register Empty
(THRE) indicator It indicates that the UART is ready
to accept a new character for transmission In addi-
tion it causes the UART to issue an interrupt to the
CPU when the Transmit Holding Register Empty In-
terrupt enable is set high The THRE bit is set to 1
when a character is transferred from the Transmitter
Holding Register into the Transmitter Shift Register
The bit is reset to 0 whenever the CPU loads the
Transmitter Holding Register In the FIFO mode it is
set when the XMIT FIFO is empty it is cleared when
at least 1 byte is written to the XMIT FIFO
This bit is the Transmitter Empty (TEMT) indicator It
is set to 1 whenever the Transmitter Holding Regis-
ter (THR) and the Transmitter Shift Register (TSR)
are both empty It is reset to 0 if either the THR or
TSR contains a data character In the FIFO mode
this bit is set to 1 whenever the transmitter FIFO and
the shift register are both empty
In the NS16450 Mode this is 0 In the FIFO Mode
this bit is set when there is at least one parity error
framing error or break indication in the FIFO It is
cleared when the CPU reads the LSR if there are no
subsequent errors in the FIFO
Note The Line Status Register is intended for read operations
Writing a 1 to FCR0 enables both the XMIT and
RCVR FIFOs Resetting FCR0 clears all bytes in
both FIFOs When changing from FIFO Mode to
NS16450 Mode and vice versa data is automati-
cally cleared from the FIFOs This bit must al-
ready be 1 when other FCR bits are written to or
they will not be programmed
Writing 1 to FCR1 clears all bytes in the RCVR
FIFO and resets its counter logic to 0 The shift
register is not cleared The 1 that is written to this
bit position is self-clearing
Writing 1 to FCR2 clears all bytes in the XMIT
FIFO and resets its counter logic to 0 The shift
register is not cleared The 1 that is written to this
bit position is self-clearing
Writing to FCR3 does not change UART opera-
tions
Receiver Line Status interrupt whenever any of the corre-
sponding conditions are detected and the interrupt is en-
abled
only Writing to this register is not recommended as this
operation is only used for factory testing In the FIFO mode
the software must load a data byte in the Rx FIFO via the
Loopback Mode in order to write to LSR2–LSR4 LSR0 and
LSR7 can’t be written to in the FIFO Mode