PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 30

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

3 0 FDC Register Description
D4–2
D1 0
3 1 5 Main Status Register (MSR)
The read-only Main Status Register (MSR) indicates the cur-
rent status of the disk controller The MSR is always avail-
able to be read One of its functions is to control the flow of
data to and from the Data Register (FIFO) The MSR indi-
cates when the disk controller is ready to send or receive
data through the Data Register It should be read before
each byte is transferred to or from the Data Register except
during a DMA transfer No delay is required when reading
this register after a data transfer
After a hardware or software reset or recovery from a pow-
er-down state the MSR is immediately available to be read
by the
circuit has stabilized and the internal registers have been
initialized When the FDC is ready to receive a new com-
mand it reports an 80h to the P The system software can
poll the MSR until it is ready The worst case time allowed
for the MSR to report an 80h value (RQM set) is 2 5 s after
reset or power-up
MSR
D7
DESC
RESET
COND
Bit 7
TAPESEL1
X
0
0
1
1
TABLE 3-4 Tape Drive Assignment Values
Request for Master Indicates that the controller is
ready to send or receive data from the P through
the FIFO This bit is cleared immediately after a byte
transfer and is set again as soon as the disk con-
troller is ready for the next byte During a Non-DMA
Execution phase the RQM indicates the status of
the interrupt pin
Reserved These bits are ignored
Tape Select 1 0 These bits assign a logical drive
number to a tape drive Drive 0 is not available as a
tape drive and is reserved as the floppy disk boot
drive See Table 3-4 for the tape drive assignment
values
RQM
P It contains a value of 00h until the oscillator
0
0
1
1
D7
0
TABLE 3-3 Media ID Bit Functions
DIO
D6
0
Bit 6
X
0
1
0
1
NON
DMA
D5
0
TAPESEL0
PROG
CMD
D4
0
Bit 5
0
1
0
1
1
0
0
0
0
BUSY
DRV3
D3
0
DRV2
BUSY
D2
0
Media Type
Invalid Data
Selected
2 88M
1 44M
5 25
720k
DRV1
BUSY
Drive
None
D1
Read Only
0
(Continued)
1
2
3
BUSY
DRV0
D0
0
30
D6
D5
D4
D3
D2
D1
D0
3 1 6 Data Rate Select Register (DSR)
This write-only register is used to program the data rate
amount of write precompensation power-down mode and
software reset The data rate is programmed via the CCR
not the DSR for PC-AT Model 30 and MicroChannel appli-
cations Other applications can set the data rate in the DSR
The data rate of the floppy controller is determined by the
most recent write to either the DSR or CCR The DSR is
unaffected by a software reset A hardware reset sets the
DSR to 02h which corresponds to the default write precom-
pensation setting and a 250 kbps data rate
DSR
D7
D6
D5
DESC
RESET
COND
RESET POWER
S W
Data I O (Direction) Indicates whether the con-
troller is expecting a byte to be written to (0) or read
from (1) the Data Register
Non-DMA Execution Indicates that the controller
is in the Execution Phase of a byte transfer opera-
tion in the Non-DMA mode This mode can be used
for multiple byte transfers by the
tion Phase via interrupts or software polling
Command in Progress This bit is set after the first
byte of the Command Phase is written This bit is
cleared after the last byte of the Result Phase is
read If there is no Result Phase in a command the
bit is cleared after the last byte of the Command
Phase is written
Drive 3 Busy Set after the last byte of the Com-
mand Phase when a Seek or Recalibrate command
is issued for drive 3 Cleared after reading the first
byte in the Result Phase of the Sense Interrupt
Command for this drive
Drive 2 Busy Same as D3 above but for drive 2
Drive 1 Busy Same as D3 above but for drive 1
Drive 0 Busy Same as D3 above but for drive 0
Software Reset This bit has the same function as
the DOR RESET (D2 see Section 3 3) except that
this software reset is self-clearing
Low Power Placing a 1 in this bit puts the control-
ler into the Manual Low Power mode The oscillator
and data separator circuits are turned off Manual
Low Power can also be accessed via the Mode
command The chip comes out of low power after a
software reset or access to the Data Register or
Main Status Register
Undefined Should be set to 0
D7
0
LOW
D6
0
D5
0
0
COMP2 COMP1 COMP0
PRE-
D4
0
PRE-
D3
0
PRE-
D2
0
P in the Execu-
DRATE1 DRATE0
D1
1
Write Only
D0
0