PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 63

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

5 0 FDC Functional Description
5 7 DATA RATE SELECTION
The data rate can be chosen two different ways with the
FDC For PC compatible software the Configuration Control
Register at address 3F7h is used to program the data rate
for the floppy controller The lower bits D1 and D0 are used
in the CCR to set the data rate The other bits should be set
to zero See Table 3-7 for the data rate select encoding
The data rate can also be set using the Data Rate Select
Register at address 4 Again the lower two bits of the regis-
ter are used to set the data rate The encoding of these bits
is exactly the same as those in the CCR The remainder of
the bits in the DSR are used for other functions Consult the
Register Description (Section 3 1 6) for more details
The data rate is determined by the last value that is written
to either the CCR or the DSR In other words either the
CCR or the DSR can override the data rate selection of the
other register When the data rate is selected the micro-
engine and data separator clocks are scaled appropriately
Also the DRATE0 and DRATE1 output pins will reflect the
state of the data select bits that were last written to either
the CCR or the DSR
5 8 WRITE PRECOMPENSATION
Write precompensation is a way of preconditioning the
WDATA output signal to adjust for the effects of bit shift on
the data as it is written to the disk surface Bit shift is caused
by the magnetic interaction of data bits as they are written
to the disk surface and has the effect of shifting these data
bits away from their nominal position in the serial MFM data
pattern Data that is subject to bit shift is much harder to
read by a data separator and can cause soft read errors
Write precompensation predicts where bit shift could occur
within a data pattern It then shifts the individual data bits
early late or not at all such that when they are written to
the disk the resultant shifted data bits will be back in their
nominal position
The FDC supports software programmable write precom-
pensation Upon power-up the default write precomp val-
ues will be used (see Table 3-6) The programmer can
choose a different value of write precomp with the DSR
register if desired (see Table 3-7) Also on power-up the
default starting track number for write precomp is track zero
This starting track number for write precomp can be
changed with the Configure command
5 9 FDC LOW POWER MODE LOGIC
The FDC section of the PC87332 supports two low power
modes described here in detail Other low power modes of
the PC87332 are described in Section 2 6 Details concern-
ing entering and exiting low power mode via setting Data
Rate Select Register bit 6 or by executing the FDC Mode
FIGURE 5-3 Perpendicular Recording Drive R W Head and Pre-Erase Head
(Continued)
63
Command are covered in this section in Section 3 1 6 and
Section 4 1 6 The microcode is driven from the clock so it
will be disabled while the clock is off The FDC clock is
always disabled upon entering this mode however the os-
cillator is only disabled when PTR1
power-down state the RQM (Request For Master) bit in the
MSR will be cleared
There are two modes of low power in the floppy controller
manual low power and automatic low power Manual low
power is enabled by writing a 1 to bit 6 of the DSR The chip
will go into low power immediately This bit will be cleared to
0 after the chip is brought out of low power Manual low
power can also be accessed via the Mode command The
function of the manual low power mode is a logical OR func-
tion between the DSR low power bit and the Mode com-
mand manual low power bit setting
Automatic low power mode will switch the controller into low
power 500 ms (at the 500 kbps MFM data rate) after it has
entered the idle state Once the auto low power mode is set
it does not have to be set again and the controller will auto-
matically go into low power mode after it has entered the
idle state Automatic low power mode can only be set with
the Mode command
There are two ways the FDC section of the SuperI O can
recover from the power-down state 1) The part will power-
up after a software reset via the DOR or DSR Since a soft-
ware reset requires reinitialization of the controller this
method can be undesirable 2) The part will also power-up
after a read or write to either the Data Register or Main
Status Register This is the preferred method of power-up
since all internal register values are retained It may take a
few milliseconds for the oscillator to stabilize and the
will be prevented from issuing commands during this time
through the normal Main Status Register protocol That is
the RQM bit in the MSR will be a 0 until the oscillator has
stabilized When the controller has completely stabilized
from power-up the RQM bit in the MSR is set to 1 and the
controller can continue where it left off
The Data Rate Select Digital Output and Configuration
Control Registers are unaffected by the power-down mode
They will remain active It is up to the user to ensure that the
Motor and Drive Select signals are turned off
Note If the power to an external oscillator driving the PC87334 is to be
5 10 RESET OPERATION
The floppy controller can be reset by hardware or software
Hardware reset is enacted by pulsing the Master Reset in-
put pin A hardware reset will set all of the user addressable
registers and internal registers to their default values The
independently removed during the FDC low power mode it must not
be done until 2 ms after the FDC low power command is issued
e
1 Upon entering the
TL C 11930 – 10
P