PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 23

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

2 0 Configuration Registers
2 5 3 Power and Test Register (PTR Index
This register determines the power-down method used
when the power-down pin (PWDN) is asserted (crystal and
clocks vs clocks only) and whether hardware power-down
is enabled It also provides a bit for software power-down of
all enabled functions It selects whether IRQ7 or IRQ5 is
associated with LPTB It puts the enabled UARTs into their
test mode
Independent of this register the floppy disk controller can
enter low power mode via the Mode Command or the Data
Rate Select Register
Bit 0 Setting this bit causes all enabled functions to be
Bit 1 When the Power-Down pin or Bit 0 is asserted this bit
Bit 2 Reserved This bit must be set to 0
Bit 3 Setting this bit associates the parallel port with IRQ7
Bit 4 Setting this bit puts UART1 into a test mode which
Bit 5 Setting this bit puts UART2 into a test mode which
Bit 6 Setting this bit to 1 prevents all further write accesses
Bit 7 When not in EPP or ECP modes this bit selects Com-
powered-down
If the crystal power-down option is selected (see Bit 1)
the crystal is also powered-down All register data is
retained when the crystal or clocks are stopped The
FDC UARTs IDE and Parallel Port pins are affected
by this bit when the relevant PMC register bits are set
Note Bits 2 and 3 of PCR can affect the function of the parallel port
determines whether the enabled functions have their
internal clocks stopped (Bit 1
crystal (Bit 1
the lowest power consumption state of the part How-
ever if the crystal is stopped a finite amount of time
( E 8 ms) is required for crystal stabilization once the
Power-Down pin (PWDN) or Bit 0 is deasserted If all
internal clocks are stopped but the crystal continues
to oscillate no stabilization period is required after the
Power-Down pin or Bit 0 is deasserted
when the address for the parallel port is 378– 37Fh
(LPTB) This bit is a ‘‘don’t care’’ when the parallel
port address is 3BC–3BEh (LPTA) or 278– 27Fh
(LPTC)
causes its Baud Out clock to be present on its SOUT1
pin if the Line Control Register bit 7 is set to 1
causes its Baud Out clock to be present on its SOUT2
pin if the Line Control Register bit 7 is set to 1
to the Configuration Registers Once it is set by soft-
ware it can only be cleared by a hardware reset After
the initial hardware reset it is zero
patible or Extended mode operation and thus controls
whether Pulse or Level interrupts are used
Set this bit to 0 for Compatible mode Pulse interrupt
Set this bit to 1 for Extended mode Level interrupt
In EPP mode this bit selects Regular or Automatic
bidirectional mode thus determining the direction
control method
Set this bit to 0 for Automatic mode Host RD and WR
signals control the direction
Set this bit to 1 for Regular mode bit 5 of CTR con-
trols the direction
After the initial hardware reset this bit is 0
power-down mode
e
1) is stopped Stopping the crystal is
e
0) or the external
e
(Continued)
02h)
23
2 5 4 Function Control Register (FCR Index
This register determines several pin options
It selects between Data Rate output and automatic media
sense inputs
It enables the Parallel Port Multiplexor (PPM) and switches
between internal and external drives
For Enhanced Parallel Port operation it enables the
IOCHRDY and ZWS options and pins
On reset bits 2 – 7 of FCR are cleared
Bit 0 Media Sense Data Rate select bit When this bit is 0
Bit 1 Reserved
Bit 2 Printer Floppy Parallel Port Multiplexor (PPM) enable
Bit 3 Parallel Port Multiplexor (PPM) float control bit When
Bit 4 Logical Drive Exchange bit This bit allows software to
FCR
Bit 4 MTR1 MTR0 DRVSEL1 DRVSEL0
0
0
1
1
the MSEN0– 1 pins are Media Sense inputs and bits
5 – 7 of TDR are valid When this bit is 1 the
DRATE0– 1 pins are Data Rate outputs and bits 2– 7
of TDR are TRI-STATE during read On reset the
VLD0 pin is sampled and its value placed into this bit
bit When this bit is 0 the port is configured as a paral-
lel port When this bit is 1 the port is configured as a
floppy drive port See PNF pin description for further
information The DRV2 PNF pin is read as DRV2 bit
regardless of bit 2 of FCR
this bit is 0 the PPM pins are driven When this bit is
1 the PPM pins are in TRI-STATE mode and the pull-
ups are disconnected
Bit 3 is functional whether or not the PPM is config-
ured (when bit 2 of FCR is 0)
When bit 3
and the inputs are blocked to reduce their leakage
current
BUSY
Note To avoid undefined FDC inputs the PPM can be disabled be-
exchange the physical floppy-disk control signals as-
signed to drives 0 and 1 thus exchanging the logical
drives A and B
This is accomplished by exchanging control of the
DR0 and MTR0 pins with the DR1 and MTR1 pins
The result is undefined if four drive mode is selected
(FER4
tween the Configuration Register bit the Digital Out-
put Register bits (DRVSEL0 1 and MTR0 1) and the
drive and motor control pins (DR0 1 and MTR0 1)
0
1
0
1
fore this bit is set
TABLE 2-9 Logical Drive Exchange
Digital Output Register (FDC)
e
e
1 PE
The values of the blocked inputs are
1) Table 2-9 shows the associations be-
e
1
0
1
0
e
1 the PPM outputs are in TRI-STATE
0 SLCT
0
0
0
0
e
0 ACK
e
0
1
0
1
1 and ERR
e
Asserted
FDC Pins
DR0
MTR0
DR1
MTR1
DR1
MTR1
DR0
MTR0
03h)
e
1