PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 24

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

2 0 Configuration Registers
Bit 5 Zero Wait State enable bit If this bit is 1 (and pin 3 1
Bit 6 ZWS PWDN select bit When this bit is 0 the ZWS
Bit 7 IOCHRDY MFM select bit When this bit is 0 the
2 5 5 Printer Control Register (PCR Index
This register enables the EPP ECP version modes and
interrupt options On reset all the PCR bits are cleared to 0
The parallel port mode is software configurable as follows
Bit 0 EPP enable bit When this bit is 0 the EPP is disabled
Bit 1 EPP version select bit When this bit is 0 Version 1 7 is
Bit 2 ECP enable bit When this bit is 0 the ECP is disabled
Bit 3 ECP Clock Freeze Control Bit In power-down modes
Bit 4 Reserved This bit must be set to 0
Bit 5 Parallel port interrupt (IRQ5 or IRQ7) polarity control
None
Compatible
Extended
EPP
ECP
Operation
and the EPP registers are not accessible (access ig-
nored)
When this bit is 1 and bit 2 of PCR is 0 the EPP is
enabled Note that the EPP should not be configured
with base address 3BCh
supported
When this bit is 1 Version 1 9 is supported (IEEE
1284)
and in power mode The ECP registers are not acces-
sible (access ignored) the ECP interrupt is inactive
and the DMA request pin is in TRI-STATE The IRQ5 7
inputs are blocked to reduce their leakage currents
When this bit is 1 the ECP is enabled The software
should change this bit to 1 only when bits 0 1 and 2 of
the existing CTR are 1 0 and 0 respectively
2 and 3 When this bit is 0 the clock provided to the
ECP is stopped and
When this bit is 1 the clock provided to the ECP is not
stopped
Note When either this bit or the ECP enable bit is 0 there is no
bit
Mode
(PQFP TQFP) is configured as ZWS) ZWS is driven
low when the Enhanced Parallel Port (EPP) or the
ECP can accept a short host read write-cycle other-
wise the ZWS open drain output is not driven EPP
ZWS operation should be configured when the sys-
tem is fast enough to support it
pin is Zero Wait State output
When this bit is 1 the PWDN CSOUT pin option is
selected
IOCHRDY pin is the IOCHRDY open drain output that
extends the host-EPP cycle when required
When this bit is 1 the MFM pin is selected
change in the PC87334 crystal stopping mechanism
TABLE 2-10 Parallel Port Mode
Bit 0
FER
0
1
1
1
1
Bit 7
PTR
X
X
X
0
1
PCR
Bit 0
X
0
0
1
0
e
(Continued)
04h)
Bit 2
PCR
X
0
0
0
1
24
Bit 6 Parallel port interrupt (IRQ5 or IRQ7) open drain con-
Bit 7 Reserved
2 5 6 Power Management Control Register
(PMC Index
This register controls the TRI-STATE and input pins The
PMC Register is accessed through Index 06h The PMC
Register is cleared to 0 on reset
Bit 0 IDE TRI-STATE control bit When this bit is 1 and ei-
Bit 1 FDC TRI-STATE control bit When this bit is 1 and the
Bit 2 UARTs TRI-STATE control bit When this bit is 1 and
Bit 3 ECP DMA configuration bit When this bit is 0 ECP
Note This bit must not be set when the PC87332 is assembled into a
Bit 4 PD and IDLE (FDC power management output pins)
Bit 5 Selective Lock bit This bit enables locking of the fol-
PC87312 PC87322 socket in which pin 33 is V
trol bit
When this bit is 0 the configured interrupt line (IRQ5
or IRQ7) has a totem-pole TRI-STATE output
When this bit is 1 the configured interrupt line has an
open drain output (drive low or TRI-STATE no drive
high no internal pullup)
SuperI O devices this bit must not be modified when
this register is written Use read-modify-write to pre-
serve the value of this bit
ther the IDE is disabled or the SuperI O is in power-
down mode HCS0 and HCS1 are in TRI-STATE
IDED7 input is also blocked to reduce leakage current
and its value is undefined when IDE is disabled
FDC is powered-down the FDC outputs are in TRI-
STATE (except IRQ6 PD IDLE and the PPM outputs
even if the PPM is used as FDC pins) and the FDC
inputs (except DSKCHG) are blocked to reduce their
leakage current
any UART is powered-down the outputs of that UART
are in TRI-STATE (except IRQ3 and IRQ4) and the
inputs are blocked to reduce their leakage current
The values of the blocked inputs are SIN
DSR
DMA is not configura ble IDENT PDACK is assumed
to be 1 and PDRQ is in TRI-STATE
When this bit is 1 ECP DMA is configurable via an
ECP control register Pins 54 and 33 are PDACK and
PDRQ respectively IDENT is assumed to be 1
enable bit
When this bit is 0 pins 43 and 45 are MTR1 and DR1
respectively
When this bit is 1 pins 43 and 45 are IDLE and PD
respectively
lowing configuration bits bit 5 of PMC bit 4 of FER
bits 0 – 7 of FAR bits 2– 3 of PTR bits 6 – 7 of FCR
and bit 0 of TUP Unlike bit 6 of PTR it does not lock
all the configuration bits
Once this bit is set by software it can only be cleared
by a hardware reset This bit should be used instead of
bit 6 of PTR if a configuration bit should be dynamically
modified by software (like PMC bits)
When this bit is 0 the interrupt polarity is as already
defined and the ECP interrupt is level high or nega-
tive pulse
When this bit is 1 the interrupt polarity is inverted
e
1 DCD
e
06h)
To maintain compatibility with future
e
1 and RI
e
1
DD
A
e
1 CTS
e
1