PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 25

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

2 0 Configuration Registers
Bit 6 Parallel Port Multiplexor (PPM) TRI-STATE enable bit
Bit 7 Reserved
2 5 7 Tape UARTs and Parallel Port Configuration
Register (TUP Index
The TUP Register is cleared to 0XX0000X on reset
Bit 0 CLK48 Clock divider enable bit
Bit 1 FDC’s 2 Mbps enable bit
Bit 2 EPP Timeout Interrupt Enable bit
Bit 3 UART 1 clock divisor control (MIDI baud rate configu-
This bit enables reduction in power consumption
(when the SuperI O is in power-down mode or the par-
allel port is disabled) by placing the PPM outputs in
TRI-STATE and blocking the PPM inputs
When this bit is 0 the parallel port pins are enabled
When this bit is 1 and either the parallel port is dis-
abled or the SuperI O is in power-down mode the out-
puts of the Parallel Port pins (except IRQ5 and IRQ7)
are in TRI-STATE and the inputs are blocked to re-
duce their leakage currents
The values of the blocked inputs are BUSY
PE
SuperI O devices this bit must not be modified when
this register is written Use read-modify-write to pre-
serve the value of this bit
When a 48 MHz clock is used this bit should be 1
When a 24 MHz clock is used this bit should be 0
When this bit is 0 the clock for all the PC87332 mod-
ules is X1 OSC (i e 24 MHz)
When this bit is 1 the clock of all PC87332 modules
except the FDC is X1 OSC divided by 2 (i e 48 2
24 MHz) and the FDC clock depends on bit 1 of TUP
During reset the value of CLK48 pin (pin 57) is latched
into this bit
This bit should not be modified by the user
When this bit is 0 a 2 Mbps data rate is not supported
by the FDC and the FDC clock is 24 MHz (X1 OSC
when bit 0 of TUP is 0 or X1 OSC divided by 2 when
bit 0 of TUP is 1)
When this bit is 1 2 Mbps is supported by the FDC
and the FDC clock is 48 MHz (X1 OSC when bit 0 of
TUP is 1) Bit 0 of TUP must be set to 1 and a 48 MHz
clock must be used to support a 2 Mbps data rate The
operating voltage should be 5V (See Section 5 0 FDC
Functional Description )
When this bit is 0 the EPP timeout interrupt is masked
When this bit is 1 the EPP timeout interrupt is generat-
ed on the selected IRQ line (IRQ5 or IRQ7) according
to PCR 6
ration) bit
When this bit is 0 the UART 1 Baud Rate Generator is
fed by the master clock divided by 13
When this bit is 1 the UART 1 Baud Rate Generator is
fed by the master clock divided by 12 This bit should
be set to 1 to support MIDI baud rates
When this bit is 0 bit 6 of PTR can be used to lock all
configuration registers
When this bit is 1 the above configuration bits cannot
be modified A hardware reset clears this bit
e
0 SLCT
To maintain compatibility with future
e
0 ACK
e
07h)
e
1 and ERR
e
1
(Continued)
e
e
1
25
Bit 4 UART 2 clock divisor control (MlDI baud rate configu-
Bit 5 PD status bit This bit holds the FDC power-down
Bit 6 IDLE status bit This bit holds the FDC idle state as
Bit 7 IDLE pin mask bit This bit masks the IDLE output pin
2 5 8 SuperI O Identification Register
(SID Index
The SID Register is accessed like the other configuration
registers through the Index Register This read-only register
is used to identify the PC87332 device
2 6 POWER-DOWN OPTIONS
The PC87332 places special emphasis on power manage-
ment Power management methods can be divided into two
major groups
Group 1 Full device power-down the entire PC87332
Group 2 Specific function power-down specific SuperI O
All power-down modes are enhanced by a new feature
which allows the output pins associated with a specific func-
tion (FDC UART1 UART2 IDE Parallel Port) to be TRI-
STATE pins and reduces current leakage by blocking their
inputs
Four modules in the PC87332 are operated by the internal
clock FDC UART1 UART2 and ECP These modules can
be powered-down or disabled by stopping their associated
internal clocks In addition all four modules can be
powered-down or disabled by stopping the external crystal
oscillator
Modules which do not use a clock the IDE and Parallel Port
(SPP EPP) can be powered-down or disabled by simply
blocking access to them
All the above power-down modes can be achieved using
the power-down methods from Group 1 or Group 2 as de-
scribed in the following sections
7
0
ration) bit
When this bit is 0 the UART 2 Baud Rate Generator is
fed by the master clock divided by 13
When this bit is 1 the UART 2 Baud Rate Generator is
fed by the master clock divided by 12 This bit should
be set to 1 to support MIDI baud rates
state as defined for the PD pin even when pin 45 is
not configured as PD This bit is read only
defined for the IDLE pin even when pin 43 is not con-
figured as IDLE and when IDLE is masked by bit 7 of
TUP This bit is read only
(but not the IDLE status bit) This bit is ignored when
pin 43 is not configured as idle
When this bit is 0 the IDLE output pin is unmasked
The IDLE pin drives the value of the FDC idle state
When this bit is 1 the IDLE output pin is masked The
IDLE pin is driven low
6
0
SuperI O is powered-down and thus disabled
modules (FDC UART1 UART2 IDE ECP or Par-
allel Port) are powered-down and thus disabled
5
0
e
08h)
4
1
3
X
X
2
1
X
0
X
Super I O Identification
Index
Reg (SID)
e
08h