PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 9

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

A10 –A0
ACK
AFD
AEN
ASTRB
BADDR0 1
BOUT1 2
BUSY
CFG0 –4
CLK48
CTS1 2
D7 –D0
Symbol
1 0 Pin Description
65 66 71
21–31
10–17
55 58
73 65
73 74
72 64
Pin
85
78
20
81
84
57
I O
I O
I O
O
O
I
I
I
I
I
I
I
I
Address These microprocessor address lines determine which internal register is accessed A0–
A10 are don’t cares during a DMA transfer
Acknowledge This input is pulsed low by a connected printer to indicate that it has received data
from the parallel port This pin has a nominal 25 k
shared with DR1 See Table 7-5 for further information )
Automatic Feed XT When this signal is low the connected printer should automatically line feed
after each line is printed This pin is in a TRI-STATE condition 10 ns after a 0 is loaded into the
corresponding Control Register bit The system should pull this pin high using a 4 7 k
(See DSTRB and Table 7-5 for further information )
Address Enable This input disables function selection via A10– A0 when it is high Access during
DMA transfer is NOT affected by this pin
Address Strobe This signal is used in EPP mode as an address strobe It is active low (See
SLIN and Table 7-5 for further information )
Base Address These bits determine one of four base addresses from which the Index and Data
Registers are offset (See Table 2-2) An internal pull-down resistor of 30 k
Use a 10 k
BAUD Output This multi-function pin provides the associated serial channel Baud Rate generator
output signal when test mode is selected in the Power and Test Configuration Register and the
DLAB bit (LCR7) is set After Master Reset this pin provides the SOUT function (See SOUT and
CFG0–4 for further information )
Busy This pin is set high by the printer when it cannot accept another character It has a nominal
25 k
Configuration on Power-up These CMOS inputs select 1 of 32 default configurations in which
the PC87334VLJ PC87334VJG powers-up (See Table 2-1) An internal pull-down resistor of 30
k
Clock 48 This pin is the CLK48 reset strap option During reset the value of this pin is latched into
bit 0 of TUP (CLK48 bit) A 30 k
resistor to pull it high during reset
Clear to Send When low this indicates that the MODEM or data set is ready to exchange data
The CTS signal is a MODEM status input whose condition the CPU can test by reading bit 4 (CTS)
of the MODEM Status Register (MSR) for the appropriate serial channel Bit 4 is the complement
of the CTS signal Bit 0 (DCTS) of the MSR indicates whether the CTS input has changed state
since the previous reading of the MSR CTS has no effect on the transmitter
Note Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled
Data Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB These
signals all have 24 mA (sink) buffered outputs
(Continued)
is present on each pin Use a 10 k
pull-down resistor attached to it (See WAIT and Table 7-5 for further information )
TABLE 1-1 Pin Descriptions (Alphabetical)
resistor to pull this pin to V
9
internal pull-down resistor is present on this pin Use a 10 k
CC
resistor to pull these pins to V
Function
pull-up resistor attached to it (This pin is
CC
is present on this pin
resistor