PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 68

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

(FIFO Mode
6 0 Serial Ports
Bits 6 7 The combination of FCR6 and FCR7 is used to
6 6 INTERRUPT IDENTIFICATION REGISTER (IIR)
In order to provide minimum software overhead during data
character transfers the UART prioritizes interrupts into four
levels and records these in the Interrupt Identification Reg-
ister The four levels of interrupt conditions in order of priori-
ty are Receiver Line Status Received Data Ready Trans-
mitter Holding Register Empty and MODEM Status
Only)
Bit 3
0
0
0
1
0
0
Interrupt Identification
7
0
0
1
1
FIGURE 6-2 Receiver FIFO Trigger Level
FCR Bits
6 2 ) When the number of bytes in the RCVR FIFO
designate the interrupt trigger level (see Figure
equals the designated interrupt trigger level a Re-
ceived Data Available Interrupt is activated This
interrupt must be enabled by setting the Interrupt
Enable Register (IER) bit 0
Bit 2
Register
0
1
1
1
0
0
6
0
1
0
1
Bit 1
0
1
0
0
1
0
(Continued)
Bit 0
1
0
0
0
0
0
Trigger Level (Bytes)
TABLE 6-5 PC87332 Interrupt Control Functions
RCVR FIFO
Priority
Highest Receiver Line Status
Second Received Data Available Receiver Data Available
Second Character
(FIFO
mode
only)
Fourth MODEM Status
Level
Third
01
04
08
14
None
Time-Out
Indication
Transmitter Holding
Register Empty
Interrupt Type
68
Interrupt Set and Reset Functions
When the CPU accesses the IIR the UART freezes all inter-
rupts and indicates to the CPU which pending interrupt has
the highest priority While the CPU accesses this interrupt
routine the UART records new interrupts but does not
change its current indication until the current access is com-
plete Table 6-2 shows the contents of the IIR Details on
each bit follow
Bit 0
Bits 1 2 These two bits of the IIR are used to identify the
Bit 3
Bits 4 5 These bits of the IIR are always 0
Bits 6 7 These two bits are set when FCR0
None
Overrun Error Parity Error
Framing Error or Break
Interrupt
No Characters have been
removed from or input to the
RCVR FIFO during the last 4
char times and there is at least
1 char in it during this time
Transmitter Holding
Register Empty
Clear to Send or Data Set
Ready or Ring Indicator
or Data Carrier Detect
This bit can be used in an interrupt environment to
indicate whether an interrupt condition is pending
When it is 0 an interrupt is pending and the IIR
contents may be used as a pointer to the appropri-
ate interrupt service routine When it is 1 no inter-
rupt is pending See Table 6-5
highest priority interrupt pending as indicated in
Table 6-5
In the 16450 mode this bit is 0 In the FIFO mode it
is set along with bit 2 when a time-out interrupt is
pending See Table 6-5
Mode enabled )
Interrupt Source
Interrupt Reset Control
Reading the Line
Status Register
Read Receiver Buffer
Reading the Receiver
Buffer Register
Reading the IIR Register
(if Source of Interrupt) or
Writing the Transmitter
Holding Register
Reading the MODEM
Status Register
e
1 (FIFO