PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 26

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

Method
2 0 Configuration Registers
2 6 1 Recommended Power-Down Methods Group 1
Use the power-down methods in Group 1 to place the
PC87332 in one of the following modes
Mode 1
Mode 2
Mode 3
Mode 4
There are 13 methods to reach the above four operating
modes See Table 2-11
2 6 2 Recommended Power-Down Methods Group 2
Use the power-down modes in Group 2 to place the
PC87332 in any desired combination of the following power-
down modes
Mode 1
Mode 2
Mode 3
Mode 4
See also the PMC register
Note 1 The PC87332 can also be placed in Mode 2 or Mode 4 using the strap configuration pins CFG0–4 (see Table 2-1)
Note 2 The PC87332 can also be placed in Mode 2 by using method
Note 3 Pin
Note 4 These values are measured under the following conditions
Note 5 UARTS should be in 16550 (FIFO) mode bit 0 of FIFO Control Register should be 1
10
11
12
13
1
2
3
4
5
6
7
8
9
high
1 No load on outputs
2 Inputs are stable
3 V
4 V
5 Using a crystal for the 24 MHz clock
The entire chip is powered-down the crystal osci-
IIator is stopped pins are TRI-STATE and the in-
puts are blocked
In this mode the maximum current saving can be
achieved
The entire chip is powered-down the crystal os-
cillator is stopped Pins are driven
The entire chip is powered-down pins are TRI-
STATE and the inputs are blocked The crystal
oscillator operates and provides fast wake-up
The entire chip is powered-down Pins are driven
The crystal oscillator operates
IL
DD
Parallel Port (SPP EPP ECP) is powered-down
providing a savings of up to 5 mA
UARTs are powered-down providing a savings of
up to 5 mA
FDC is powered-down providing a savings of up
to 4 mA
IDE is powered-down providing a savings of up
to 0 1 mA
PTR Bits 012
3 is PDWN input (configured when bit 2 of PTR is 0 and bit 6 of FCR is 1)
e
e
V
3 3V
SS
11x
x10
11x
x10
10x
x00
10x
x00
x1x
x1x
x1x
x0x
x0x
V
IH
e
V
DD
(Note 3)
TABLE 2-11 Methods to Achieve Group 1 Power-Down Modes
Pin 3
0
0
0
0
x
x
x
x
x
x
x
x
x
FER Bits 01236
00000
00000
00000
00000
(Continued)
xxxxx
xxxxx
xxxxx
xxxxx
xxx1x
xxxxx
xxxxx
xxxxx
xxxxx
7 and entering FDC Low Power by executing Mode Command or by setting bit 6 of DSR to
PCR Bit 2
26
0
0
0
0
x
x
x
x
x
x
x
x
x
2 7 POWER-UP PROCEDURE AND CONSIDERATIONS
2 7 1 Crystal Stabilization
If the crystal is stopped by putting either the FDC or both
UARTs into low power mode then a finite amount of time
( E 8 ms) must be allowed for crystal stabilization during
subsequent power-up The stabilization period can be
sensed by reading the Main Status Register in the FDC if
the FDC is being powered up (The Request for Master bit is
not set for E 8 ms ) If either one of the UARTs are being
powered up but the FDC is not then the software must
determine the E 8 ms crystal stabilization period Stabiliza-
tion of the crystal can also be sensed by putting the UART
into local loopback mode and sending bytes until they are
received correctly
2 7 2 UART Power-Up
The clock signal to the UARTs is controlled through the
Configuration Registers (FER PTR) In order to restore the
clock signal to one or both UARTs the following conditions
must exist
1 The appropriate enable bit (FER1 2) for the UART(s)
2 The Power-Down bit (PTR0) must not be set
3 If the PWDN pin option (PTR2 and FCR6) is used the
If the crystal has been stopped follow the guidelines in
Section 2 7 1 before sending data or signaling that the re-
ceiver channel is ready
must be set
CSOUT PWDN ZWS pin must be inactive
PMC Bits 0126
1111
1111
1111
0000
0000
0000
0000
1111
1111
1111
0000
0000
0000
(Notes 1 2)
(Note 1)
Mode
1
2
3
4
Typical Current
Consumption
(Notes 4 5)
10 A
30 A
4 mA
4 mA