PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 34

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

4-1
3 0 FDC Register Description
D2
D1
D0
3 2 4 Status Register 3 (ST3)
D7
D6
D5
D4
D3
D2
D1–0
4 0 FDC Command Set Description
This section presents the FDC command set full descrip-
tion in Section 4 1 and a working summary in Section 4 2
Each command contains a unique first command byte the
opcode byte which tells the controller how many (0 or
more) command bytes to expect The information for each
command is displayed using the structure shown in Figure
If an invalid command byte is issued to the controller it
immediately enters the Result Phase and the status is 80h
signifying an Invalid Command
4 1 COMMAND DESCRIPTIONS
4 1 1 Configure Command
The Configure Command controls some operation modes of
the controller It should be issued during the initialization of
the FDC after power-up These bits are set to their default
values after a hardware reset The value of each bit after a
software reset is explained The default value of each bit is
denoted by a ‘‘bullet’’ to the left of each item
DESC
RESET
COND
Scan Not Satisfied Controller cannot find a sector
on the track which meets the desired condition dur-
ing any Scan command
Bad Track Only set if the desired sector is not
found the track number recorded on any sector on
the track is FFh indicating a hard error in IBM for-
mat and is different from the track address speci-
fied in the Command Phase
Missing Address Mark in Data Field Controller
cannot find the Data Field Address Mark (AM) dur-
ing a Read Scan or Verify command Bit 0 of ST1
is also set
Not Used Always 0
Write Protect Indicates active high status of the
WP pin
Not Used Always 1
Track 0 Indicates active high status of the TRK0
pin
Not Used Always 1
Head Select Indicates the active high status of the
HD bit in the Command Phase
Drive Select 1 0 These two binary encoded bits
indicate the DS1–0 bits in the Command Phase
FIGURE 4-1 FDC Command Structure
D7
0
0
WP
D6
0
I O Operation
Command Byte 1
Command Byte 2
Command Byte n
D5
1
1
Opcode
TK0
D4
0
D3
1
1
HDS
D2
0
DS1
D1
0
(Continued)
DS0
D0
0
34
Command Phase
Execution Phase Internal registers written
Result Phase None
EIS Enable Implied Seeks Default after a software reset
FIFO Enable FIFO for Execution Phase data transfers De-
POLL Disable for Drive Polling Mode Default after a soft-
THRESH The FIFO threshold in the Execution Phase of
PRETRK Starting track number for write precompensation
4 1 2 Dumpreg Command
The Dumpreg command is designed to support system run-
time diagnostics application software development and de-
bug This command has a one-byte command phase and a
10-byte result phase The Result Phase returns the values
of parameters set in other commands That is the PTR
(Present Track Register) contains the least significant byte
of the track the microcode has stored for each drive The
Step Rate Time Motor Off and Motor On Times and the
DMA bit are all set in the Specify command
0
0
0
0
1
1
fault after a software reset if the LOCK bit is 0 If the
LOCK bit is 1 then the FIFO bit retains its previous
value after a software reset
0
e
e
0
ware reset
1
e
e
EIS
e
e
Implied seeks disabled through Configure com-
mand Implied seeks can still be enabled through
the Mode command when EIS
Implied seeks enabled for a read write scan or
verify operation A seek and sense interrupt oper-
ation is performed prior to the execution of the
read write scan or verify operation The IPS bit
does not need to be set
0
0
read and write data transfers Programmable
from 00h to 0Fh Defaults to 00h after a software
reset if the LOCK bit is 0 If the LOCK bit is 1
THRESH retains its value A high value of
THRESH is suited for slow response systems
and a low value of THRESH is better for fast re-
sponse systems
Programmable from track 0 (‘‘00’’) to track 255
(‘‘FF’’) Defaults to track 0 (‘‘00’’) after a software
reset if the LOCK bit is 0 If the LOCK bit is 1
then PRETRK retains its value
FIFO disabled
FIFO enabled for both reads and writes
Enable drive polling mode An interrupt is gener-
ated after a reset
Disable drive polling mode If the Configure
command is issued within 500 s of a hardware
or software reset then an interrupt is not gener-
ated In addition the use of the four Sense In-
terrupt commands to clear the ‘‘Ready Changed
State’’ of the four logical drives is not required
FIFO
0
0
PRETRK
POLL
1
0
0
0
e
THRESH
0
0
0
1
0
1
0