PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 28

PC87332VLJ-5

Manufacturer Part Number

PC87332VLJ-5

Description

PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac

Manufacturer

NSC [National Semiconductor]

Datasheet

1.PC87332VLJ-5.pdf (98 pages)

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3 0 FDC Register Description

3 1 1 Status Register A (SRA)

This read-only diagnostic register is part of the PS 2 floppy

controller register set and is enabled when in the PS 2 or

Model 30 mode This register monitors the state of the IRQ6

pin and some of the disk interface signals The SRA can be

read at any time when in PS 2 mode In the PC-AT mode

D7 –D0 are TRI-STATE during a P read

SRA PS 2 Mode

SRA

A2 A1 A0 IDENT R W

Note SRA and SRB are enabled by IDENT

DESC

RESET

COND

DESC

RESET

COND

TABLE 3-1 Register Description and Addresses

Interrupt Pending This active high bit reflects the

state of the IRQ6 pin

2nd Drive Installed

DRV2 disk interface input indicating if a second

drive has been installed

Step Active high status of the STEP disk interface

output

Track 0 Active low status of the TRK0 disk inter-

face input

Head Select Active high status of the HDSEL disk

interface output

Index Active low status of the INDEX disk interface

input

Write Protect Active low status of the WP disk in-

terface input

Direction Active high status of the DIR disk inter-

face output

Model 30 Mode

Interrupt Pending This active high bit reflects that

state of the IRQ6 pin

DMA Request Active high status of the DRQ signal

Step Active high status of the latched STEP disk

interface output This bit is latched with the STEP

output going active and is cleared with a read from

the DIR or with a hardware or software reset

PEND

IRQ6

DRV2

DRQ

N A

R W Digital Output Register

R W Tape Drive Register

R W Data Register (FIFO)

STEP

Status Register A

Status Register B

Main Status Register

Data Rate Select Register

None (Bus TRI-STATE)

Digital Input Register

Configuration Control Register CCR

TRK0

N A

Active low status of the

HDSEL

0 during a chip reset only

INDX

N A

Read Only

(Continued)

N A

DOR

MSR

FIFO

SRA

SRB

TDR

DSR

DIR

3 1 2 Status Register B (SRB)

This read-only diagnostic register is part of the PS 2 floppy

controller register set and is enabled when in the PS 2 or

Model 30 mode The SRB can be read at any time when in

PS 2 mode In the PC-AT mode D7– D0 are TRI-STATE

during a P read

SRB PS 2 Mode

SRB Model 30 Mode

DESC

RESET

COND

DESC

RESET

COND

Track 0 Active high status of TRK0 disk interface

input

Head Select Active low status of the HDSEL disk

interface output

Index Active high status of the INDEX disk inter-

face input

Write Protect Active high status of the WP disk

interface input

Direction Active low status of the DIR disk inter-

face output

Reserved Always 1

Drive Select 0 Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2 bit 0) It is cleared

after a hardware reset not a software reset

Write Data Every inactive edge transition of the

WDATA disk interface output causes this bit to

change states

Read Data Every inactive edge transition of the

RDATA disk interface output causes this bit to

change states

Write Gate Active high status of the WGATE disk

interface output

Motor Enable 1 Active high status of the MTR1

disk interface output Low after a hardware reset

unaffected by a software reset

Motor Enable 0 Active high status of the MTR0

disk interface output Low after a hardware reset

unaffected by a software reset

2nd Drive Installed

DRV2 disk interface input

Drive Select 1 Active low status of the DR1 disk

interface output

Drive Select 0 Active low status of the DR0 disk

interface output

N A N A

DRV2

N A

DR1

DR0 WDATA RDATA WGATE MTR1 MTR0

DR0

WDATA

Active low status of the

RDATA

WGATE

Read Only

DR3

DR2

PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 28

PC87332VLJ-5

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