PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 60

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

5 0 FDC Functional Description
5 3 2 3 Interrupt Mode FIFO Disabled
If the Interrupt (Non-DMA) mode is selected IRQ6 is assert-
ed instead of DRQ when each byte is ready to be trans-
ferred The Main Status Register should be read to verify
that the interrupt is for a data transfer The RQM and non-
DMA bits (D7 and D5) in the MSR are set The interrupt is
cleared when the byte is transferred to or from the Data
Register CS and RD or CS and WR must be used to trans-
fer the data in or out of the Data Register (A2–A0 must be
valid) CS asserted by itself is not significant CS must be
asserted with RD or WR for a read or write transfer to be
recognized
The
service time (see Section 3 7) If the byte is not transferred
within the time allotted an Overrun Error is indicated in the
Result Phase when the command terminates at the end of
the current sector
An interrupt is also generated after the last byte is trans-
ferred This indicates the beginning of the Result Phase
The RQM and DIO bits (D7 and D6) in the MSR are set and
the non-DMA bit (D5) is cleared This interrupt is cleared by
reading the first Result Phase byte
5 3 2 4 Interrupt Mode FIFO Enabled
The Interrupt (Non-DMA) mode with the FIFO enabled is
very similar to the Non-DMA mode with the FIFO disabled
In this case IRQ6 is asserted instead of DRQ under the
exact same FIFO threshold trigger conditions The MSR
should be read to verify that the interrupt is for a data trans-
fer The RQM and non-DMA bits (D7 and D5) in the MSR
are set CS and RD or CS and WR must be used to transfer
the data in or out of the Data Register (A2–A0 must be
valid) CS asserted by itself is not significant CS must be
asserted with RD or WR for a read or write transfer to be
recognized
The Burst mode may be used to hold the IRQ6 pin active
during a burst or the Non-Burst mode may be used to tog-
gle the IRQ6 pin for each byte of a burst The Main Status
Register is always valid from the
ample during a read command after the last byte of data
has been read from the disk and placed in the FIFO the
MSR still indicates that the Execution Phase is active and
that data needs to be read from the Data Register Only
after the last byte of data has been read by the P from the
FIFO does the Result Phase begin
The same overrun and underrun error procedures from the
DMA mode apply to the Non-DMA mode Also whether
there is an error or not an interrupt is generated at the end
of the Execution Phase and is cleared by reading the first
Result Phase byte
5 3 2 5 Software Polling
If the Non-DMA mode is selected and interrupts are not
suitable the
Phase to determine when a byte is ready to be transferred
The RQM bit (D7) in the MSR reflects the state of the IRQ6
signal Otherwise the data transfer is similar to the Interrupt
Mode described above This is true for the FIFO enabled or
disabled
5 3 3 Result Phase
During the Result Phase the
from the data register These bytes indicate the status of the
command This status may indicate whether the command
executed properly or it may contain some control informa-
P should transfer the byte within the data transfer
P can poll the MSR during the Execution
P reads a series of bytes
P point of view For ex-
(Continued)
60
tion (see the Command Description Section 4 1 and Status
Register Description Section 3 0) These Result Phase
bytes are read in the order specified for that particular com-
mand Some commands do not have a result phase Also
the number of result bytes varies with each command All of
the result bytes must be read from the Data Register before
the next command can be issued
Like the Command Phase the Main Status Register con-
trols the flow of result bytes and must be polled by the
software before reading each Result Phase byte from the
Data Register The RQM bit (D7) and DIO bit (D6) must both
be set before each result byte can be read After the last
result byte is read the COM PROG bit (D4) in the MSR is
cleared and the controller is ready for the next command
5 3 4 Idle Phase
After a hardware or software reset or after the chip has
recovered from the power-down mode the controller enters
the Idle Phase Also when there are no commands in prog-
ress the controller is in the Idle Phase The controller waits
for a command byte to be written to the Data Register The
RQM bit is set and the DIO bit is cleared in the MSR After
receiving the first command (opcode) byte the controller
enters the Command Phase When the command is com-
pleted the controller again enters the Idle Phase The Data
Separator remains synchronized to the reference frequency
while the controller is idle While in the Idle Phase the con-
troller periodically enters the Drive Polling Phase (see
Section 5 3 5)
5 3 5 Drive Polling Phase
The National FDC supports the polling mode of the old gen-
eration 8-inch drives as a means of monitoring any change
in status for each disk drive present in the system This
mode is supported for the sole purpose of providing back-
ward compatibility with software that expects its presence
While in the Idle Phase the controller enters a Drive Polling
Phase every 1 ms (based on a 500 kbps data rate) While in
the Drive Polling Phase the controller interrogates the
Ready Changed status for each of the four logical drives
The internal Ready line for each drive is toggled only after a
hardware or software reset and an interrupt is generated for
drive 0 At this point the software must issue four Sense
Interrupt commands to clear the Ready Changed State
status for each drive This requirement can be eliminated if
drive polling is disabled via the POLL bit in the Configure
command The Configure command must be issued within
500
drive polling to be disabled
Even if drive polling is disabled drive stepping and delayed
power-down occur in the Drive Polling Phase The controller
checks the status of each drive and if necessary it issues a
step pulse on the STEP output with the DIR signal at the
appropriate logic level Also the controller uses the Drive
Polling Phase to control the Automatic Low Power mode
When the Motor Off time has expired the controller waits
512 ms based on a 500 kbps or 1 Mbps data rate before
powering down if this function is enabled via the Mode com-
mand
If a new command is issued when the FDC is in the middle
of a polling routine the MSR will not indicate a ready status
for the next parameter byte until the polling sequence com-
pletes the loop This can cause a delay between the first
and second bytes of up to 500 s at 250 kbps
s (worst case) of the hardware or software reset for