PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 27

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

Figure 3-1
2 0 Configuration Registers
2 7 3 FDC Power-Up
The clock signal to the FDC is controlled through the Con-
figuration Registers the FDC Mode Command and the Data
Rate Select Register In order to restore the clock signal to
the FDC the following conditions must exist
1 The appropriate enable bit (FER3) must be set
2 The Power-Down bit (PTR0) must not be set
3 If the PWDN pin option (PTR2 and FCR 6) is used the
In addition to these conditions one of the following actions
must be taken to initiate recovery from the Power-Down
mode
1 Read the Main Status Register until the RQM bit (MSR7)
2 Write to the Data Rate Select Register and set the Soft-
3 Write to the Digital Output Register clear and then set
4 Read the Data Register and the Main Status Register
If the crystal has been stopped read the RQM bit in the
Main Status Register until it is set The RQM bit is not set
until the crystal has stabilized
3 0 FDC Register Description
The floppy disk controller (FDC) is suitable for all PC-AT
EISA PS 2 and general purpose applications The opera-
tional mode (PC-AT PS 2 or Model 30) of the FDC is deter-
mined by hardware strapping of the IDENT and MFM pins
DP8473 and N82077 software compatibility is provided Key
features include a 16-byte FIFO PS 2 diagnostic register
support perpendicular recording mode CMOS disk inter-
face and a high performance digital data separator See
PWDN ZWS pin must be inactive
is set OR
ware Reset bit (DSR7) OR
the Reset bit (DOR2) OR
until the RQM bit is set
FIGURE 3-1 FDC Functional Block Diagram
(Continued)
27
The FDC supports fast 2 Mbps data rate drives and stan-
dard 1 Mbps 250 500 kbps and 300 500 kbps data rate
drives The 1 Mbps data rate is used by the high perform-
ance tape and floppy disk drives The 2 Mbps data rate is
used in very high performance tape drives The FDC also
supports the perpendicular recording mode a new format
used with some high performance high capacity disk drives
at the 1 Mbps data rate
The high performance internal digital data separator needs
no external components It improves on the window margin
performance standards of the DP8473 and is compatible
with the strict data separator requirements of floppy disk
and floppy-tape drives
The FDC contains write precompensation circuitry that de-
faults to 125 ns for 250 kbps 300 kbps and 500 kbps to
41 67 ns for 1 Mbps and to 20 8 ns for 2 Mbps These
values can be overridden in software to disable write pre-
compensation or to provide levels of precompensation up to
250 ns
The FDC has internal 24 mA data bus buffers which allow
direct connection to the system bus The internal 40 mA
totem-pole disk interface buffers are compatible with both
CMOS drive inputs and 150
inputs
3 1 FDC CONTROL REGISTERS
The following FDC registers are mapped into the addresses
shown in Table 3-1 and described in the following sections
The base address range is provided by the on-chip address
decoder pin For PC-AT or PS 2 applications the diskette
controller primary address range is 3F0h to 3F7h and the
secondary address range is 370h to 377h The FDC sup-
ports three different register modes the PC-AT mode PS 2
mode (MicroChannel systems) and the Model 30 mode
See Section 5 2 for more details on how each register mode
is enabled When applicable the register definition for each
mode of operation is given
If no special notes are made then the register is valid for all
three register modes
resistor terminated disk drive
TL C 11930 – 6