SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 90

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

TRS … Timer Resolution
RAC … Receiver Active
RTS … Request To Send
TMD … Timer Mode
TLP … Test Loop
Semiconductor Group
The resolution of the internal timer (factor k, see description of TIMR register) is selected
0 …
1 …
Switches the receiver to inoperational state.
0 … HDLC receiver inactive
1 … HDLC receiver active
In extended transparent modes this bit must be reset to enable fully transparent reception!
Defines the state and control of RTS pin.
0 … The RTS pin is controlled by the HSCX autonomously.
RTS is activated when a frame transmission starts and deactivated after the transmission
operation is completed.
1 … The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains active till this bit is reset
(not valid in bus configuration).
RxD is disconnected from the mechanical pin and internally connected to TxD of the same
channel. TxD pin remains active.
The operation mode of the internal timer is set.
0 … external mode
The timer is controlled by the CPU and can be started at any time setting the STI bit in
CMDR.
1 … internal mode
The timer is used internally by the HSCX for time-out and retry conditions in auto-mode.
(refer to the description of the TIMR register)
k
k
= 32.768
= 512
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SAB 82525
SAB 82526
SAF 82525
SAF 82526