SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 59

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

– Phase Shift
In the case the DPLL detects an edge in the data stream in the range of DPLL count 5 to 10
(Phase Shift) and this is the only one in the assumed bit cell period, then the DPLL receive
clock phase is shifted by a certain DPLL count value.
Figure 28d
Synchronization of the Data Clock in DPLL Mode: Interference Rejection and Phase
Adjustment
The DPLL value and its corresponding phase shift in degree is listed below for the HSCX
versions VA3 and V2.1:
Note: The operating characteristics of the DPLL therefore allow a phase jitter of 18.75% of the
Semiconductor Group
HSCX Version
VA3
V2.1
Phase Shift
DPLL Input
Receive Data
DPLL Count
DPLL
Phase Correction
DPLL Output
Receive Clock
frequency.
0
DPLL Count
8
7
1
Phase Adjust
2
3
+
1
4
5
59
6
Phase Shift
157,5
180
Assumed Bit Cell
-
Phase Shift
7
o
o
8
+
7
9
+
10
11 12
Phase Adjust
13
1 -
14
SAB 82525
SAB 82526
SAF 82525
SAF 82526
ITD05884
15