SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 10

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

P-LCC P-MQFP
1.1 Pin Definitions and Functions
Pin No.
42
43
44
Semiconductor Group
1
2
3
4
5
6
7
8
3
4
5
6
7
8
9
10
11
12
13
Symbol
D0
D1
D2
D3
D4
D5
D6
D7
RD/IC1
WR/IC0 I
CS
Input (I)
Output (O)
I/O
I
I
Function
Data Bus
The data bus lines are bidirectional threestate lines which
interface with the system’s data bus.
These lines carry data and command/status to and from
the HSCX.
Read, Intel bus mode, IM1 connected to low
This signal indicates a read operation. When the HSCX is
selected via CS the read signal enables the bus drivers to
put data from an internal register addressed via A0-A6 on
the data bus.
When the HSCX is selected for DMA transfers via DACK,
the RD signal enables the bus driver to put data from the
respective receive FIFO on the data bus. Inputs to A0-A6
are ignored.
Input Control 1, Motorola bus mode IM1 connected to
high.
If Motorola bus mode has been selected this pin serves
either as
E = Enable, active high (IM0 tied to low) or
DS = Data Strobe, active low (IM0 tied to high)
input (depending on the selection via IM0) to control read/
write operations.
Write, Intel bus mode
This signal indicates a write operation. When CS is active
the HSCX loads an internal register with data provided via
the data bus. When DACK is active for DMA transfers the
HSCX loads data from the data bus on the top of the
respective transmit FIFO.
Input Control Motorola bus mode
In Motorola bus mode, this pin serves as the R/W input to
distinguish between read or write operations.
Chip Select
A low signal selects the HSCX for a read/write operation.
10
SAB
SAB
SAF
SAF
82525
82526
82525
82526