SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 55

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

CTS Signal in Clock Mode 5
In clock mode 5 the CTS signal is evaluated not only in the time-slot “window“, but also
between the time-slot “windows“. If data transmission must not be stopped, CTS has to be
active, even between the time-slot “windows“, until the transmission of the frame has been
completed. In other words, a deactivation of CTS stops the transmitter immediately.
Note: When several HDLC channels are sharing the same time-slot on a bus without using
Clock Mode 6 (OSC – Receive Clock from DPLL)
This clock mode equals the features of Clock Mode 2, with the only exception that the clock for
the BRG is delivered by the OSC and must not be provided externally.
Clock Mode 7 (OSC – Receive and Transmit Clock from DPLL)
Similar to Clock Mode 3, but BRG clock is provided by OSC.
Semiconductor Group
the bus collision detection, the strobe signals (AxCLKA/B) can be used to select/
deselect particular time-slot “windows“ for an individual HDLC channel.
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SAB 82525
SAB 82526
SAF 82525
SAF 82526