SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 60

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

5.3 Bus Configuration
Beside the point-to-point configuration, the HSCX effectively supports point-to-multipoint (pt-
mpt, or bus) configurations by means of internal idle and collision detection/collision resolution
methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral stations
(slaves), or in a multimaster configuration (see figure 6), data transmission can be initiated by
each station over a common transmit line (bus). In case more than one station attempt to
transmit data simultaneously (collision), the bus is assigned to one station by a collision-
resolution procedure implemented by the HSCX. The bus assignment function is based on a
priority principle with both fixed and rotating priorities that enables each station to access the
bus in a predeterminable time. As a result, any number of transmitters can be connected to the
serial bus.
Prerequisites for bus operation are:
The bus configuration is selected via the CCR1 register.
Note: Central clock supply for each station is not necessary if both the receive and transmit
Semiconductor Group
– NRZ encoding
– OR connection of data at the bus
– feedback of bus information (C DA/C DB input)
clock is recovered by the DPLL (clock mode 7). In this case, the function of the DPLL
also minimizes the phase shift between the transmit clocks of the individual transmitters
so that an opening flag sequence will be sufficient to allow a correct collision detection.
The bus mode can be operated independently of the clock mode, e.g. also during clock
mode 1 (receive and transmission strobe) or clock mode 5 (programmable time-slots).
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SAB 82525
SAB 82526
SAF 82525
SAF 82526