SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 87

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

RMC … Receive Message Complete
Note:
RHR … Reset HDLC Receiver
RNR/XREP … Receiver Not Ready/Transmission Repeat
Together with XTF and XME set (write 2 A
contents of the XFIFO (1 … 32 bytes) without HDLC framing fully transparent, i.e. without
FLAG, CRC insertion, bit stuffing.
The cyclic transmission is stopped with an XRES command!
Command Register (WRITE)
Value after RESET: 00
CMDR
Note:
Semiconductor Group
Confirmation from CPU to HSCX, that the actual frame or data block has been fetched
following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released.
All data in the RFIFO and the HDLC receiver deleted.
In auto-mode, additionally the transmit and receive sequence number counters are reset.
The function of this command depends on the selected operation mode (MDS1, MDS0,
ADM bit in MODE):
The status of the HSCX receiver is set. Determines, whether a received frame is
acknowledged via an RR, or RNR supervisory frame in auto-mode.
0 … Receiver Ready (RR)
1 … Receiver Not Ready (RNR)
Auto-mode: RNR
Extended transparent mode 0, 1 : XREP
In DMA mode, this command is only issued once after a RME interrupt. The HSCX does
not generate further DMA requests prior to the reception of this command.
The maximum time between writing to the CMDR register and the execution of the
command is 2.5 clock cycles. Therefore, if the CPU operates with a very high clock in
comparison with the HSCX’s clock, it's recommended that the CEC bit of the STAR
register is checked before writing to the CMDR register to avoid any loss of commands.
7
RMC
RHR
H
XREP
RNR
STI
H
87
to CMDR), the HSCX repeatedly transmits the
XTF
XIF
XME
XRES
SAB 82525
SAB 82526
SAF 82525
SAF 82526
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