SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 67

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

6.5 One Bit Insertion
Similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the HDLC protocol, the
HSCX offers a completely new feature of inserting/deleting a one after seven consecutive
zeros in the transmit/receive data stream, if the serial channel is operating in a bus
configuration.
This method is profitable if clock recovery should be performed by DPLL.
Since only NRZ data encoding is supported in a bus configuration (see chapter 5.4), there are
possibly long sequences without edges in the receive data stream in case of successive "0"-s
received, and the DPLL may loose synchronization.
Using the one bit insertion feature by setting the OIN bit in the CCR1 register, however, it is
guaranteed that at least after
– 5 consecutive "1"-s a "0" will appear (bit-stuffing), and
– 7 consecutive "0"-s a "1" will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As with the bit-stuffing, this method is fully transparent to the user, but it is not in
6.6 Data Inversion
When NRZ data encoding has been selected, the HSCX may transmit and receive data
inverted, i.e. a
"one" bit is transmitted as phys. zero (0 V) and a "zero" bit as phys. one (+ 5 V) via the T D line.
This feature is selected by setting the DIV bit in the CCR2 register.
Please note that data cannot be inverted in bus mode unless you invert the T D / R D signal
before it is sent into C D.
Semiconductor Group
accordance with the HDLC protocol, i.e. it can only be applied in private systems using
HSCX circuits exclusively.
Log. Data Bit
1
0
Transmit
Receive
67
+
5
0
V
V
Phys. Level
ITD00245
SAB 82525
SAB 82526
SAF 82525
SAF 82526