SAF82525 Infineon Technologies AG, SAF82525 Datasheet - Page 44

• Manufacturer Part Number: SAF82525
• Description: Data Communications ICs
• Manufacturer: Infineon Technologies AG

HSCX supports target synchronous as well as source synchronous DMA transfer. In source
synchronous DMA transfer mode a DMA cycle is started when an active level occurs an the
DMA request line. This request is controlled by the source (transfer peripheral device
memory).
First of all the data is read out of the peripheral device. During the second clock cycle it is writ-
ten into the memory according to the target address.
If there is target synchronous DMA transfer the DMA cycle is started when there is an active
level on the DMA request line. The request is controlled by the target (transfer memory
peripheral).
First of all the data is read from the memory. During the second clock cycle it is written into the
peripheral IC. The DMA request line continues being activated until it is reset by a write cycle
to a peripheral device IC.
Semiconductor Group
CLOCKOUT
DRQ
RD
(FIFO)
(Memory)
t
f
12.5
16
WR
8 MHz
DRHSYS
CLKOUT
MHz
MHz
max
=
T2
t
125 ns
+
80
62.5
CLCL
T3
ns
ns
+
T4
t -
t
CLRL
CLRL
T1
t
44 ns
37
31
CLRL
t -
ns
ns
INVCL
T2
t
DRHSYS
=
t
15 ns
15
15
x 3
INVCL
T3
ns
ns
t
CLCL
44
t
INVCL
T4
- t
CLRL
t
DRHSYS max
316 ns
188
141.5
t -
T1
ns
INVCL
ns
T2
T3
T4
SAB 82525
SAB 82526
SAF 82525
SAF 82526
ITD02697